|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc12874 { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12877 { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12880 { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12883 { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12886 { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12889 { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12892 { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12895 { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12898 { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12901 { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12904 { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12907 { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12910 { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12913 { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12916 { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12919 { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12946 { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12949 { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12952 { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12955 { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12958 { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12961 { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12964 { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12967 { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12970 { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12973 { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12976 { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12979 { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12982 { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12985 { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12988 { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12991 { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12994 { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12997 { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13000 { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13003 { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13006 { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13009 { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13012 { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13015 { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13018 { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13021 { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13024 { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13027 { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13030 { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13033 { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13036 { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13039 { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13042 { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13045 { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13048 { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13051 { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_ci, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13054 { 4573 /* flat_load_dword */, AMDGPU::FLAT_LOAD_DWORD_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13057 { 4589 /* flat_load_dwordx2 */, AMDGPU::FLAT_LOAD_DWORDX2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13060 { 4607 /* flat_load_dwordx3 */, AMDGPU::FLAT_LOAD_DWORDX3_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_96, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13063 { 4625 /* flat_load_dwordx4 */, AMDGPU::FLAT_LOAD_DWORDX4_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_128, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13066 { 4643 /* flat_load_sbyte */, AMDGPU::FLAT_LOAD_SBYTE_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13077 { 4745 /* flat_load_sshort */, AMDGPU::FLAT_LOAD_SSHORT_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13080 { 4762 /* flat_load_ubyte */, AMDGPU::FLAT_LOAD_UBYTE_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13087 { 4821 /* flat_load_ushort */, AMDGPU::FLAT_LOAD_USHORT_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13090 { 4838 /* flat_store_byte */, AMDGPU::FLAT_STORE_BYTE_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13095 { 4877 /* flat_store_dword */, AMDGPU::FLAT_STORE_DWORD_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13098 { 4894 /* flat_store_dwordx2 */, AMDGPU::FLAT_STORE_DWORDX2_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13101 { 4913 /* flat_store_dwordx3 */, AMDGPU::FLAT_STORE_DWORDX3_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_96, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13104 { 4932 /* flat_store_dwordx4 */, AMDGPU::FLAT_STORE_DWORDX4_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13107 { 4951 /* flat_store_short */, AMDGPU::FLAT_STORE_SHORT_ci, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX7Only, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
29842 { 3983 /* flat_atomic_add */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29843 { 3983 /* flat_atomic_add */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29848 { 3983 /* flat_atomic_add */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29849 { 3983 /* flat_atomic_add */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29854 { 3999 /* flat_atomic_add_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29855 { 3999 /* flat_atomic_add_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29860 { 3999 /* flat_atomic_add_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29861 { 3999 /* flat_atomic_add_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29866 { 4018 /* flat_atomic_and */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29867 { 4018 /* flat_atomic_and */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29872 { 4018 /* flat_atomic_and */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29873 { 4018 /* flat_atomic_and */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29878 { 4034 /* flat_atomic_and_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29879 { 4034 /* flat_atomic_and_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29884 { 4034 /* flat_atomic_and_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29885 { 4034 /* flat_atomic_and_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29890 { 4053 /* flat_atomic_cmpswap */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29891 { 4053 /* flat_atomic_cmpswap */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29896 { 4053 /* flat_atomic_cmpswap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29897 { 4053 /* flat_atomic_cmpswap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29902 { 4073 /* flat_atomic_cmpswap_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29903 { 4073 /* flat_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29908 { 4073 /* flat_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29909 { 4073 /* flat_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29914 { 4096 /* flat_atomic_dec */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29915 { 4096 /* flat_atomic_dec */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29920 { 4096 /* flat_atomic_dec */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29921 { 4096 /* flat_atomic_dec */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29926 { 4112 /* flat_atomic_dec_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29927 { 4112 /* flat_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29932 { 4112 /* flat_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29933 { 4112 /* flat_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29986 { 4250 /* flat_atomic_inc */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29987 { 4250 /* flat_atomic_inc */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29992 { 4250 /* flat_atomic_inc */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29993 { 4250 /* flat_atomic_inc */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
29998 { 4266 /* flat_atomic_inc_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
29999 { 4266 /* flat_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30004 { 4266 /* flat_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30005 { 4266 /* flat_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30010 { 4285 /* flat_atomic_or */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30011 { 4285 /* flat_atomic_or */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30016 { 4285 /* flat_atomic_or */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30017 { 4285 /* flat_atomic_or */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30022 { 4300 /* flat_atomic_or_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30023 { 4300 /* flat_atomic_or_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30028 { 4300 /* flat_atomic_or_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30029 { 4300 /* flat_atomic_or_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30034 { 4318 /* flat_atomic_smax */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30035 { 4318 /* flat_atomic_smax */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30040 { 4318 /* flat_atomic_smax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30041 { 4318 /* flat_atomic_smax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30046 { 4335 /* flat_atomic_smax_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30047 { 4335 /* flat_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30052 { 4335 /* flat_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30053 { 4335 /* flat_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30058 { 4355 /* flat_atomic_smin */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30059 { 4355 /* flat_atomic_smin */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30064 { 4355 /* flat_atomic_smin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30065 { 4355 /* flat_atomic_smin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30070 { 4372 /* flat_atomic_smin_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30071 { 4372 /* flat_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30076 { 4372 /* flat_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30077 { 4372 /* flat_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30082 { 4392 /* flat_atomic_sub */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30083 { 4392 /* flat_atomic_sub */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30088 { 4392 /* flat_atomic_sub */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30089 { 4392 /* flat_atomic_sub */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30094 { 4408 /* flat_atomic_sub_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30095 { 4408 /* flat_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30100 { 4408 /* flat_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30101 { 4408 /* flat_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30106 { 4427 /* flat_atomic_swap */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30107 { 4427 /* flat_atomic_swap */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30112 { 4427 /* flat_atomic_swap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30113 { 4427 /* flat_atomic_swap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30118 { 4444 /* flat_atomic_swap_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30119 { 4444 /* flat_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30124 { 4444 /* flat_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30125 { 4444 /* flat_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30130 { 4464 /* flat_atomic_umax */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30131 { 4464 /* flat_atomic_umax */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30136 { 4464 /* flat_atomic_umax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30137 { 4464 /* flat_atomic_umax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30142 { 4481 /* flat_atomic_umax_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30143 { 4481 /* flat_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30148 { 4481 /* flat_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30149 { 4481 /* flat_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30154 { 4501 /* flat_atomic_umin */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30155 { 4501 /* flat_atomic_umin */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30160 { 4501 /* flat_atomic_umin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30161 { 4501 /* flat_atomic_umin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30166 { 4518 /* flat_atomic_umin_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30167 { 4518 /* flat_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30172 { 4518 /* flat_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30173 { 4518 /* flat_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30178 { 4538 /* flat_atomic_xor */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30179 { 4538 /* flat_atomic_xor */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30184 { 4538 /* flat_atomic_xor */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30185 { 4538 /* flat_atomic_xor */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30190 { 4554 /* flat_atomic_xor_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30191 { 4554 /* flat_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30196 { 4554 /* flat_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30197 { 4554 /* flat_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30202 { 4573 /* flat_load_dword */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30203 { 4573 /* flat_load_dword */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30204 { 4573 /* flat_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30205 { 4573 /* flat_load_dword */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30214 { 4589 /* flat_load_dwordx2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30215 { 4589 /* flat_load_dwordx2 */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30216 { 4589 /* flat_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30217 { 4589 /* flat_load_dwordx2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30226 { 4607 /* flat_load_dwordx3 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30227 { 4607 /* flat_load_dwordx3 */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30228 { 4607 /* flat_load_dwordx3 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30229 { 4607 /* flat_load_dwordx3 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30238 { 4625 /* flat_load_dwordx4 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30239 { 4625 /* flat_load_dwordx4 */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30240 { 4625 /* flat_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30241 { 4625 /* flat_load_dwordx4 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30250 { 4643 /* flat_load_sbyte */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30251 { 4643 /* flat_load_sbyte */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30252 { 4643 /* flat_load_sbyte */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30253 { 4643 /* flat_load_sbyte */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30294 { 4745 /* flat_load_sshort */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30295 { 4745 /* flat_load_sshort */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30296 { 4745 /* flat_load_sshort */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30297 { 4745 /* flat_load_sshort */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30306 { 4762 /* flat_load_ubyte */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30307 { 4762 /* flat_load_ubyte */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30308 { 4762 /* flat_load_ubyte */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30309 { 4762 /* flat_load_ubyte */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30334 { 4821 /* flat_load_ushort */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30335 { 4821 /* flat_load_ushort */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30336 { 4821 /* flat_load_ushort */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30337 { 4821 /* flat_load_ushort */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30346 { 4838 /* flat_store_byte */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30347 { 4838 /* flat_store_byte */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30348 { 4838 /* flat_store_byte */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30349 { 4838 /* flat_store_byte */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30366 { 4877 /* flat_store_dword */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30367 { 4877 /* flat_store_dword */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30368 { 4877 /* flat_store_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30369 { 4877 /* flat_store_dword */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30378 { 4894 /* flat_store_dwordx2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30379 { 4894 /* flat_store_dwordx2 */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30380 { 4894 /* flat_store_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30381 { 4894 /* flat_store_dwordx2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30390 { 4913 /* flat_store_dwordx3 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30391 { 4913 /* flat_store_dwordx3 */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30392 { 4913 /* flat_store_dwordx3 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30393 { 4913 /* flat_store_dwordx3 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30402 { 4932 /* flat_store_dwordx4 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30403 { 4932 /* flat_store_dwordx4 */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30404 { 4932 /* flat_store_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30405 { 4932 /* flat_store_dwordx4 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30414 { 4951 /* flat_store_short */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX7Only },
30415 { 4951 /* flat_store_short */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30416 { 4951 /* flat_store_short */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX7Only },
30417 { 4951 /* flat_store_short */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX7Only },