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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc12875 { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12878 { 3983 /* flat_atomic_add */, AMDGPU::FLAT_ATOMIC_ADD_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12881 { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12884 { 3999 /* flat_atomic_add_x2 */, AMDGPU::FLAT_ATOMIC_ADD_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12887 { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12890 { 4018 /* flat_atomic_and */, AMDGPU::FLAT_ATOMIC_AND_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12893 { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12896 { 4034 /* flat_atomic_and_x2 */, AMDGPU::FLAT_ATOMIC_AND_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12899 { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12902 { 4053 /* flat_atomic_cmpswap */, AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12905 { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12908 { 4073 /* flat_atomic_cmpswap_x2 */, AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12911 { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12914 { 4096 /* flat_atomic_dec */, AMDGPU::FLAT_ATOMIC_DEC_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12917 { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12920 { 4112 /* flat_atomic_dec_x2 */, AMDGPU::FLAT_ATOMIC_DEC_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12947 { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12950 { 4250 /* flat_atomic_inc */, AMDGPU::FLAT_ATOMIC_INC_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12953 { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12956 { 4266 /* flat_atomic_inc_x2 */, AMDGPU::FLAT_ATOMIC_INC_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12959 { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12962 { 4285 /* flat_atomic_or */, AMDGPU::FLAT_ATOMIC_OR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12965 { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12968 { 4300 /* flat_atomic_or_x2 */, AMDGPU::FLAT_ATOMIC_OR_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12971 { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12974 { 4318 /* flat_atomic_smax */, AMDGPU::FLAT_ATOMIC_SMAX_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12977 { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12980 { 4335 /* flat_atomic_smax_x2 */, AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12983 { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12986 { 4355 /* flat_atomic_smin */, AMDGPU::FLAT_ATOMIC_SMIN_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12989 { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12992 { 4372 /* flat_atomic_smin_x2 */, AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
12995 { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
12998 { 4392 /* flat_atomic_sub */, AMDGPU::FLAT_ATOMIC_SUB_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13001 { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13004 { 4408 /* flat_atomic_sub_x2 */, AMDGPU::FLAT_ATOMIC_SUB_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13007 { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13010 { 4427 /* flat_atomic_swap */, AMDGPU::FLAT_ATOMIC_SWAP_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13013 { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13016 { 4444 /* flat_atomic_swap_x2 */, AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13019 { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13022 { 4464 /* flat_atomic_umax */, AMDGPU::FLAT_ATOMIC_UMAX_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13025 { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13028 { 4481 /* flat_atomic_umax_x2 */, AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13031 { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13034 { 4501 /* flat_atomic_umin */, AMDGPU::FLAT_ATOMIC_UMIN_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13037 { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13040 { 4518 /* flat_atomic_umin_x2 */, AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13043 { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13046 { 4538 /* flat_atomic_xor */, AMDGPU::FLAT_ATOMIC_XOR_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13049 { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmSLC1_3, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, },
13052 { 4554 /* flat_atomic_xor_x2 */, AMDGPU::FLAT_ATOMIC_XOR_X2_RTN_gfx10, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_glc, MCK_ImmSLC }, },
13055 { 4573 /* flat_load_dword */, AMDGPU::FLAT_LOAD_DWORD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13058 { 4589 /* flat_load_dwordx2 */, AMDGPU::FLAT_LOAD_DWORDX2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13061 { 4607 /* flat_load_dwordx3 */, AMDGPU::FLAT_LOAD_DWORDX3_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_96, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13064 { 4625 /* flat_load_dwordx4 */, AMDGPU::FLAT_LOAD_DWORDX4_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_128, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13067 { 4643 /* flat_load_sbyte */, AMDGPU::FLAT_LOAD_SBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13078 { 4745 /* flat_load_sshort */, AMDGPU::FLAT_LOAD_SSHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13081 { 4762 /* flat_load_ubyte */, AMDGPU::FLAT_LOAD_UBYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13088 { 4821 /* flat_load_ushort */, AMDGPU::FLAT_LOAD_USHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VGPR_32, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13091 { 4838 /* flat_store_byte */, AMDGPU::FLAT_STORE_BYTE_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13096 { 4877 /* flat_store_dword */, AMDGPU::FLAT_STORE_DWORD_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13099 { 4894 /* flat_store_dwordx2 */, AMDGPU::FLAT_STORE_DWORDX2_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_64, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13102 { 4913 /* flat_store_dwordx3 */, AMDGPU::FLAT_STORE_DWORDX3_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_96, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13105 { 4932 /* flat_store_dwordx4 */, AMDGPU::FLAT_STORE_DWORDX4_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VReg_128, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
13108 { 4951 /* flat_store_short */, AMDGPU::FLAT_STORE_SHORT_gfx10, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_2__ImmGLC1_3__ImmSLC1_4__ImmDLC1_5, AMFBS_HasFlatAddressSpace_isGFX10Plus, { MCK_VReg_64, MCK_VGPR_32, MCK_ImmFlatOffset, MCK_ImmGLC, MCK_ImmSLC, MCK_ImmDLC }, },
29844 { 3983 /* flat_atomic_add */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29845 { 3983 /* flat_atomic_add */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29850 { 3983 /* flat_atomic_add */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29851 { 3983 /* flat_atomic_add */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29856 { 3999 /* flat_atomic_add_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29857 { 3999 /* flat_atomic_add_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29862 { 3999 /* flat_atomic_add_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29863 { 3999 /* flat_atomic_add_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29868 { 4018 /* flat_atomic_and */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29869 { 4018 /* flat_atomic_and */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29874 { 4018 /* flat_atomic_and */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29875 { 4018 /* flat_atomic_and */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29880 { 4034 /* flat_atomic_and_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29881 { 4034 /* flat_atomic_and_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29886 { 4034 /* flat_atomic_and_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29887 { 4034 /* flat_atomic_and_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29892 { 4053 /* flat_atomic_cmpswap */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29893 { 4053 /* flat_atomic_cmpswap */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29898 { 4053 /* flat_atomic_cmpswap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29899 { 4053 /* flat_atomic_cmpswap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29904 { 4073 /* flat_atomic_cmpswap_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29905 { 4073 /* flat_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29910 { 4073 /* flat_atomic_cmpswap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29911 { 4073 /* flat_atomic_cmpswap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29916 { 4096 /* flat_atomic_dec */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29917 { 4096 /* flat_atomic_dec */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29922 { 4096 /* flat_atomic_dec */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29923 { 4096 /* flat_atomic_dec */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29928 { 4112 /* flat_atomic_dec_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29929 { 4112 /* flat_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29934 { 4112 /* flat_atomic_dec_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29935 { 4112 /* flat_atomic_dec_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29988 { 4250 /* flat_atomic_inc */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29989 { 4250 /* flat_atomic_inc */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29994 { 4250 /* flat_atomic_inc */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
29995 { 4250 /* flat_atomic_inc */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30000 { 4266 /* flat_atomic_inc_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30001 { 4266 /* flat_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30006 { 4266 /* flat_atomic_inc_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30007 { 4266 /* flat_atomic_inc_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30012 { 4285 /* flat_atomic_or */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30013 { 4285 /* flat_atomic_or */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30018 { 4285 /* flat_atomic_or */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30019 { 4285 /* flat_atomic_or */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30024 { 4300 /* flat_atomic_or_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30025 { 4300 /* flat_atomic_or_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30030 { 4300 /* flat_atomic_or_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30031 { 4300 /* flat_atomic_or_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30036 { 4318 /* flat_atomic_smax */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30037 { 4318 /* flat_atomic_smax */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30042 { 4318 /* flat_atomic_smax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30043 { 4318 /* flat_atomic_smax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30048 { 4335 /* flat_atomic_smax_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30049 { 4335 /* flat_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30054 { 4335 /* flat_atomic_smax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30055 { 4335 /* flat_atomic_smax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30060 { 4355 /* flat_atomic_smin */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30061 { 4355 /* flat_atomic_smin */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30066 { 4355 /* flat_atomic_smin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30067 { 4355 /* flat_atomic_smin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30072 { 4372 /* flat_atomic_smin_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30073 { 4372 /* flat_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30078 { 4372 /* flat_atomic_smin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30079 { 4372 /* flat_atomic_smin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30084 { 4392 /* flat_atomic_sub */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30085 { 4392 /* flat_atomic_sub */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30090 { 4392 /* flat_atomic_sub */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30091 { 4392 /* flat_atomic_sub */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30096 { 4408 /* flat_atomic_sub_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30097 { 4408 /* flat_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30102 { 4408 /* flat_atomic_sub_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30103 { 4408 /* flat_atomic_sub_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30108 { 4427 /* flat_atomic_swap */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30109 { 4427 /* flat_atomic_swap */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30114 { 4427 /* flat_atomic_swap */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30115 { 4427 /* flat_atomic_swap */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30120 { 4444 /* flat_atomic_swap_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30121 { 4444 /* flat_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30126 { 4444 /* flat_atomic_swap_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30127 { 4444 /* flat_atomic_swap_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30132 { 4464 /* flat_atomic_umax */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30133 { 4464 /* flat_atomic_umax */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30138 { 4464 /* flat_atomic_umax */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30139 { 4464 /* flat_atomic_umax */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30144 { 4481 /* flat_atomic_umax_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30145 { 4481 /* flat_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30150 { 4481 /* flat_atomic_umax_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30151 { 4481 /* flat_atomic_umax_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30156 { 4501 /* flat_atomic_umin */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30157 { 4501 /* flat_atomic_umin */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30162 { 4501 /* flat_atomic_umin */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30163 { 4501 /* flat_atomic_umin */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30168 { 4518 /* flat_atomic_umin_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30169 { 4518 /* flat_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30174 { 4518 /* flat_atomic_umin_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30175 { 4518 /* flat_atomic_umin_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30180 { 4538 /* flat_atomic_xor */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30181 { 4538 /* flat_atomic_xor */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30186 { 4538 /* flat_atomic_xor */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30187 { 4538 /* flat_atomic_xor */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30192 { 4554 /* flat_atomic_xor_x2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30193 { 4554 /* flat_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30198 { 4554 /* flat_atomic_xor_x2 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30199 { 4554 /* flat_atomic_xor_x2 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30206 { 4573 /* flat_load_dword */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30207 { 4573 /* flat_load_dword */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30208 { 4573 /* flat_load_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30209 { 4573 /* flat_load_dword */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30218 { 4589 /* flat_load_dwordx2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30219 { 4589 /* flat_load_dwordx2 */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30220 { 4589 /* flat_load_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30221 { 4589 /* flat_load_dwordx2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30230 { 4607 /* flat_load_dwordx3 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30231 { 4607 /* flat_load_dwordx3 */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30232 { 4607 /* flat_load_dwordx3 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30233 { 4607 /* flat_load_dwordx3 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30242 { 4625 /* flat_load_dwordx4 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30243 { 4625 /* flat_load_dwordx4 */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30244 { 4625 /* flat_load_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30245 { 4625 /* flat_load_dwordx4 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30254 { 4643 /* flat_load_sbyte */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30255 { 4643 /* flat_load_sbyte */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30256 { 4643 /* flat_load_sbyte */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30257 { 4643 /* flat_load_sbyte */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30298 { 4745 /* flat_load_sshort */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30299 { 4745 /* flat_load_sshort */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30300 { 4745 /* flat_load_sshort */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30301 { 4745 /* flat_load_sshort */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30310 { 4762 /* flat_load_ubyte */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30311 { 4762 /* flat_load_ubyte */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30312 { 4762 /* flat_load_ubyte */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30313 { 4762 /* flat_load_ubyte */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30338 { 4821 /* flat_load_ushort */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30339 { 4821 /* flat_load_ushort */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30340 { 4821 /* flat_load_ushort */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30341 { 4821 /* flat_load_ushort */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30350 { 4838 /* flat_store_byte */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30351 { 4838 /* flat_store_byte */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30352 { 4838 /* flat_store_byte */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30353 { 4838 /* flat_store_byte */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30370 { 4877 /* flat_store_dword */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30371 { 4877 /* flat_store_dword */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30372 { 4877 /* flat_store_dword */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30373 { 4877 /* flat_store_dword */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30382 { 4894 /* flat_store_dwordx2 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30383 { 4894 /* flat_store_dwordx2 */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30384 { 4894 /* flat_store_dwordx2 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30385 { 4894 /* flat_store_dwordx2 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30394 { 4913 /* flat_store_dwordx3 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30395 { 4913 /* flat_store_dwordx3 */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30396 { 4913 /* flat_store_dwordx3 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30397 { 4913 /* flat_store_dwordx3 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30406 { 4932 /* flat_store_dwordx4 */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30407 { 4932 /* flat_store_dwordx4 */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30408 { 4932 /* flat_store_dwordx4 */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30409 { 4932 /* flat_store_dwordx4 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30418 { 4951 /* flat_store_short */, 4 /* 2 */, MCK_ImmFlatOffset, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30419 { 4951 /* flat_store_short */, 32 /* 5 */, MCK_ImmDLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30420 { 4951 /* flat_store_short */, 8 /* 3 */, MCK_ImmGLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },
30421 { 4951 /* flat_store_short */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasFlatAddressSpace_isGFX10Plus },