reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
23567 { 13238 /* v_add_co_u32 */, AMDGPU::V_ADD_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7, AMFBS_HasDPP_HasDPP_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23581 { 13388 /* v_addc_co_u32 */, AMDGPU::V_ADDC_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, AMFBS_HasDPP_HasDPP_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23861 { 25975 /* v_sub_co_u32 */, AMDGPU::V_SUB_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7, AMFBS_HasDPP_HasDPP_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23875 { 26100 /* v_subb_co_u32 */, AMDGPU::V_SUBB_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, AMFBS_HasDPP_HasDPP_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23879 { 26125 /* v_subbrev_co_u32 */, AMDGPU::V_SUBBREV_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, AMFBS_HasDPP_HasDPP_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23891 { 26175 /* v_subrev_co_u32 */, AMDGPU::V_SUBREV_CO_U32_dpp_gfx9, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7, AMFBS_HasDPP_HasDPP_isGFX9Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 72893 { 13238 /* v_add_co_u32 */, 16 /* 4 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP_isGFX9Only }, 72894 { 13238 /* v_add_co_u32 */, 32 /* 5 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP_isGFX9Only }, 72895 { 13238 /* v_add_co_u32 */, 64 /* 6 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX9Only }, 72896 { 13238 /* v_add_co_u32 */, 128 /* 7 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP_isGFX9Only }, 73054 { 13388 /* v_addc_co_u32 */, 32 /* 5 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP_isGFX9Only }, 73055 { 13388 /* v_addc_co_u32 */, 64 /* 6 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP_isGFX9Only }, 73056 { 13388 /* v_addc_co_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX9Only }, 73057 { 13388 /* v_addc_co_u32 */, 256 /* 8 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP_isGFX9Only }, 79695 { 25975 /* v_sub_co_u32 */, 16 /* 4 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP_isGFX9Only }, 79696 { 25975 /* v_sub_co_u32 */, 32 /* 5 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP_isGFX9Only }, 79697 { 25975 /* v_sub_co_u32 */, 64 /* 6 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX9Only }, 79698 { 25975 /* v_sub_co_u32 */, 128 /* 7 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP_isGFX9Only }, 79847 { 26100 /* v_subb_co_u32 */, 32 /* 5 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP_isGFX9Only }, 79848 { 26100 /* v_subb_co_u32 */, 64 /* 6 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP_isGFX9Only }, 79849 { 26100 /* v_subb_co_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX9Only }, 79850 { 26100 /* v_subb_co_u32 */, 256 /* 8 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP_isGFX9Only }, 79873 { 26125 /* v_subbrev_co_u32 */, 32 /* 5 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP_isGFX9Only }, 79874 { 26125 /* v_subbrev_co_u32 */, 64 /* 6 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP_isGFX9Only }, 79875 { 26125 /* v_subbrev_co_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX9Only }, 79876 { 26125 /* v_subbrev_co_u32 */, 256 /* 8 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP_isGFX9Only }, 79942 { 26175 /* v_subrev_co_u32 */, 16 /* 4 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP_isGFX9Only }, 79943 { 26175 /* v_subrev_co_u32 */, 32 /* 5 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP_isGFX9Only }, 79944 { 26175 /* v_subrev_co_u32 */, 64 /* 6 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX9Only }, 79945 { 26175 /* v_subrev_co_u32 */, 128 /* 7 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP_isGFX9Only },