reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
23578 { 13378 /* v_add_u32 */, AMDGPU::V_ADD_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7, AMFBS_HasDPP_HasDPP_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23582 { 13402 /* v_addc_u32 */, AMDGPU::V_ADDC_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, AMFBS_HasDPP_HasDPP_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23872 { 26090 /* v_sub_u32 */, AMDGPU::V_SUB_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7, AMFBS_HasDPP_HasDPP_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23876 { 26114 /* v_subb_u32 */, AMDGPU::V_SUBB_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, AMFBS_HasDPP_HasDPP_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23880 { 26142 /* v_subbrev_u32 */, AMDGPU::V_SUBBREV_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8, AMFBS_HasDPP_HasDPP_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 23902 { 26259 /* v_subrev_u32 */, AMDGPU::V_SUBREV_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_4__ImmRowMask1_5__ImmBankMask1_6__ImmBoundCtrl1_7, AMFBS_HasDPP_HasDPP_isGFX8Only, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, }, 73036 { 13378 /* v_add_u32 */, 16 /* 4 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP_isGFX8Only }, 73037 { 13378 /* v_add_u32 */, 32 /* 5 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP_isGFX8Only }, 73038 { 13378 /* v_add_u32 */, 64 /* 6 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX8Only }, 73039 { 13378 /* v_add_u32 */, 128 /* 7 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP_isGFX8Only }, 73068 { 13402 /* v_addc_u32 */, 32 /* 5 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP_isGFX8Only }, 73069 { 13402 /* v_addc_u32 */, 64 /* 6 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP_isGFX8Only }, 73070 { 13402 /* v_addc_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX8Only }, 73071 { 13402 /* v_addc_u32 */, 256 /* 8 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP_isGFX8Only }, 79829 { 26090 /* v_sub_u32 */, 16 /* 4 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP_isGFX8Only }, 79830 { 26090 /* v_sub_u32 */, 32 /* 5 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP_isGFX8Only }, 79831 { 26090 /* v_sub_u32 */, 64 /* 6 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX8Only }, 79832 { 26090 /* v_sub_u32 */, 128 /* 7 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP_isGFX8Only }, 79861 { 26114 /* v_subb_u32 */, 32 /* 5 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP_isGFX8Only }, 79862 { 26114 /* v_subb_u32 */, 64 /* 6 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP_isGFX8Only }, 79863 { 26114 /* v_subb_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX8Only }, 79864 { 26114 /* v_subb_u32 */, 256 /* 8 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP_isGFX8Only }, 79887 { 26142 /* v_subbrev_u32 */, 32 /* 5 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP_isGFX8Only }, 79888 { 26142 /* v_subbrev_u32 */, 64 /* 6 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP_isGFX8Only }, 79889 { 26142 /* v_subbrev_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX8Only }, 79890 { 26142 /* v_subbrev_u32 */, 256 /* 8 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP_isGFX8Only }, 80072 { 26259 /* v_subrev_u32 */, 16 /* 4 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP_isGFX8Only }, 80073 { 26259 /* v_subrev_u32 */, 32 /* 5 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP_isGFX8Only }, 80074 { 26259 /* v_subrev_u32 */, 64 /* 6 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP_isGFX8Only }, 80075 { 26259 /* v_subrev_u32 */, 128 /* 7 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP_isGFX8Only },