|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc23572 { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23584 { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23588 { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23591 { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23597 { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23608 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23616 { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23619 { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23628 { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23631 { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23634 { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23637 { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23640 { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23643 { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23646 { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23649 { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23655 { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23664 { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23667 { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23673 { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23687 { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23691 { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23694 { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23697 { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23703 { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23714 { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23720 { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23726 { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23735 { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23740 { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23744 { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23748 { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23756 { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23760 { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23764 { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23770 { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23774 { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23778 { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23781 { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23784 { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23790 { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23793 { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23796 { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23799 { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23802 { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23806 { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23809 { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23812 { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23818 { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23821 { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23827 { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23833 { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23843 { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23849 { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23866 { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23896 { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23907 { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_dpp_vi, ConvertCustom_cvtDPP, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23913 { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_HasDPP_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
72953 { 13261 /* v_add_f32 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
72954 { 13261 /* v_add_f32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
72955 { 13261 /* v_add_f32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
72956 { 13261 /* v_add_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
72957 { 13261 /* v_add_f32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
73080 { 13444 /* v_and_b32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
73081 { 13444 /* v_and_b32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
73082 { 13444 /* v_and_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
73083 { 13444 /* v_and_b32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
73125 { 13503 /* v_ashrrev_i32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
73126 { 13503 /* v_ashrrev_i32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
73127 { 13503 /* v_ashrrev_i32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
73128 { 13503 /* v_ashrrev_i32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
73154 { 13586 /* v_bfrev_b32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
73155 { 13586 /* v_bfrev_b32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
73156 { 13586 /* v_bfrev_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
73157 { 13586 /* v_bfrev_b32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
73230 { 13609 /* v_ceil_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
73231 { 13609 /* v_ceil_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
73232 { 13609 /* v_ceil_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
73233 { 13609 /* v_ceil_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
73234 { 13609 /* v_ceil_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
75921 { 21959 /* v_cndmask_b32 */, 16 /* 4 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
75922 { 21959 /* v_cndmask_b32 */, 32 /* 5 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
75923 { 21959 /* v_cndmask_b32 */, 64 /* 6 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
75924 { 21959 /* v_cndmask_b32 */, 128 /* 7 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
76022 { 21983 /* v_cos_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
76023 { 21983 /* v_cos_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
76024 { 21983 /* v_cos_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
76025 { 21983 /* v_cos_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76026 { 21983 /* v_cos_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
76097 { 22045 /* v_cvt_f16_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
76098 { 22045 /* v_cvt_f16_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
76099 { 22045 /* v_cvt_f16_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
76100 { 22045 /* v_cvt_f16_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76101 { 22045 /* v_cvt_f16_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
76200 { 22087 /* v_cvt_f32_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
76201 { 22087 /* v_cvt_f32_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
76202 { 22087 /* v_cvt_f32_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
76203 { 22087 /* v_cvt_f32_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76204 { 22087 /* v_cvt_f32_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
76240 { 22115 /* v_cvt_f32_i32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
76241 { 22115 /* v_cvt_f32_i32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
76242 { 22115 /* v_cvt_f32_i32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76243 { 22115 /* v_cvt_f32_i32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
76274 { 22129 /* v_cvt_f32_u32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
76275 { 22129 /* v_cvt_f32_u32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
76276 { 22129 /* v_cvt_f32_u32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76277 { 22129 /* v_cvt_f32_u32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
76308 { 22143 /* v_cvt_f32_ubyte0 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
76309 { 22143 /* v_cvt_f32_ubyte0 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
76310 { 22143 /* v_cvt_f32_ubyte0 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76311 { 22143 /* v_cvt_f32_ubyte0 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
76342 { 22160 /* v_cvt_f32_ubyte1 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
76343 { 22160 /* v_cvt_f32_ubyte1 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
76344 { 22160 /* v_cvt_f32_ubyte1 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76345 { 22160 /* v_cvt_f32_ubyte1 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
76376 { 22177 /* v_cvt_f32_ubyte2 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
76377 { 22177 /* v_cvt_f32_ubyte2 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
76378 { 22177 /* v_cvt_f32_ubyte2 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76379 { 22177 /* v_cvt_f32_ubyte2 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
76410 { 22194 /* v_cvt_f32_ubyte3 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
76411 { 22194 /* v_cvt_f32_ubyte3 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
76412 { 22194 /* v_cvt_f32_ubyte3 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76413 { 22194 /* v_cvt_f32_ubyte3 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
76480 { 22253 /* v_cvt_flr_i32_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
76481 { 22253 /* v_cvt_flr_i32_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
76482 { 22253 /* v_cvt_flr_i32_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
76483 { 22253 /* v_cvt_flr_i32_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76484 { 22253 /* v_cvt_flr_i32_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
76546 { 22285 /* v_cvt_i32_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
76547 { 22285 /* v_cvt_i32_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
76548 { 22285 /* v_cvt_i32_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
76549 { 22285 /* v_cvt_i32_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76550 { 22285 /* v_cvt_i32_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
76635 { 22351 /* v_cvt_off_f32_i4 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
76636 { 22351 /* v_cvt_off_f32_i4 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
76637 { 22351 /* v_cvt_off_f32_i4 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76638 { 22351 /* v_cvt_off_f32_i4 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
76732 { 22543 /* v_cvt_rpi_i32_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
76733 { 22543 /* v_cvt_rpi_i32_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
76734 { 22543 /* v_cvt_rpi_i32_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
76735 { 22543 /* v_cvt_rpi_i32_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76736 { 22543 /* v_cvt_rpi_i32_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
76798 { 22575 /* v_cvt_u32_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
76799 { 22575 /* v_cvt_u32_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
76800 { 22575 /* v_cvt_u32_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
76801 { 22575 /* v_cvt_u32_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
76802 { 22575 /* v_cvt_u32_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
77027 { 22909 /* v_exp_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
77028 { 22909 /* v_exp_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
77029 { 22909 /* v_exp_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
77030 { 22909 /* v_exp_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77031 { 22909 /* v_exp_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
77074 { 22936 /* v_ffbh_i32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
77075 { 22936 /* v_ffbh_i32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
77076 { 22936 /* v_ffbh_i32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77077 { 22936 /* v_ffbh_i32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
77100 { 22947 /* v_ffbh_u32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
77101 { 22947 /* v_ffbh_u32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
77102 { 22947 /* v_ffbh_u32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77103 { 22947 /* v_ffbh_u32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
77126 { 22958 /* v_ffbl_b32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
77127 { 22958 /* v_ffbl_b32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
77128 { 22958 /* v_ffbl_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77129 { 22958 /* v_ffbl_b32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
77202 { 22981 /* v_floor_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
77203 { 22981 /* v_floor_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
77204 { 22981 /* v_floor_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
77205 { 22981 /* v_floor_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77206 { 22981 /* v_floor_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
77380 { 23180 /* v_fract_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
77381 { 23180 /* v_fract_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
77382 { 23180 /* v_fract_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
77383 { 23180 /* v_fract_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77384 { 23180 /* v_fract_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
77467 { 23224 /* v_frexp_exp_i32_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
77468 { 23224 /* v_frexp_exp_i32_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
77469 { 23224 /* v_frexp_exp_i32_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
77470 { 23224 /* v_frexp_exp_i32_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77471 { 23224 /* v_frexp_exp_i32_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
77536 { 23281 /* v_frexp_mant_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
77537 { 23281 /* v_frexp_mant_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
77538 { 23281 /* v_frexp_mant_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
77539 { 23281 /* v_frexp_mant_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77540 { 23281 /* v_frexp_mant_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
77770 { 23511 /* v_log_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
77771 { 23511 /* v_log_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
77772 { 23511 /* v_log_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
77773 { 23511 /* v_log_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77774 { 23511 /* v_log_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
77833 { 23603 /* v_lshlrev_b32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
77834 { 23603 /* v_lshlrev_b32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
77835 { 23603 /* v_lshlrev_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77836 { 23603 /* v_lshlrev_b32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
77878 { 23667 /* v_lshrrev_b32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
77879 { 23667 /* v_lshrrev_b32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
77880 { 23667 /* v_lshrrev_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77881 { 23667 /* v_lshrrev_b32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
77930 { 23705 /* v_mac_f32 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
77931 { 23705 /* v_mac_f32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
77932 { 23705 /* v_mac_f32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
77933 { 23705 /* v_mac_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
77934 { 23705 /* v_mac_f32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
78126 { 24094 /* v_max_f32 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
78127 { 24094 /* v_max_f32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
78128 { 24094 /* v_max_f32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
78129 { 24094 /* v_max_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78130 { 24094 /* v_max_f32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
78184 { 24124 /* v_max_i32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
78185 { 24124 /* v_max_i32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
78186 { 24124 /* v_max_i32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78187 { 24124 /* v_max_i32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
78232 { 24161 /* v_max_u32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
78233 { 24161 /* v_max_u32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
78234 { 24161 /* v_max_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78235 { 24161 /* v_max_u32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
78415 { 24785 /* v_min_f32 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
78416 { 24785 /* v_min_f32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
78417 { 24785 /* v_min_f32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
78418 { 24785 /* v_min_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78419 { 24785 /* v_min_f32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
78473 { 24815 /* v_min_i32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
78474 { 24815 /* v_min_i32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
78475 { 24815 /* v_min_i32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78476 { 24815 /* v_min_i32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
78521 { 24852 /* v_min_u32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
78522 { 24852 /* v_min_u32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
78523 { 24852 /* v_min_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78524 { 24852 /* v_min_u32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
78550 { 24862 /* v_mov_b32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
78551 { 24862 /* v_mov_b32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
78552 { 24862 /* v_mov_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78553 { 24862 /* v_mov_b32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
78576 { 24872 /* v_mov_fed_b32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
78577 { 24872 /* v_mov_fed_b32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
78578 { 24872 /* v_mov_fed_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78579 { 24872 /* v_mov_fed_b32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
78659 { 24999 /* v_mul_f32 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
78660 { 24999 /* v_mul_f32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
78661 { 24999 /* v_mul_f32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
78662 { 24999 /* v_mul_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78663 { 24999 /* v_mul_f32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
78701 { 25032 /* v_mul_hi_i32_i24 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
78702 { 25032 /* v_mul_hi_i32_i24 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
78703 { 25032 /* v_mul_hi_i32_i24 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78704 { 25032 /* v_mul_hi_i32_i24 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
78730 { 25062 /* v_mul_hi_u32_u24 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
78731 { 25062 /* v_mul_hi_u32_u24 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
78732 { 25062 /* v_mul_hi_u32_u24 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78733 { 25062 /* v_mul_hi_u32_u24 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
78759 { 25079 /* v_mul_i32_i24 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
78760 { 25079 /* v_mul_i32_i24 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
78761 { 25079 /* v_mul_i32_i24 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78762 { 25079 /* v_mul_i32_i24 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
78797 { 25093 /* v_mul_legacy_f32 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
78798 { 25093 /* v_mul_legacy_f32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
78799 { 25093 /* v_mul_legacy_f32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
78800 { 25093 /* v_mul_legacy_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78801 { 25093 /* v_mul_legacy_f32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
78846 { 25149 /* v_mul_u32_u24 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
78847 { 25149 /* v_mul_u32_u24 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
78848 { 25149 /* v_mul_u32_u24 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78849 { 25149 /* v_mul_u32_u24 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
78881 { 25182 /* v_not_b32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
78882 { 25182 /* v_not_b32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
78883 { 25182 /* v_not_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78884 { 25182 /* v_not_b32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
78907 { 25202 /* v_or_b32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
78908 { 25202 /* v_or_b32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
78909 { 25202 /* v_or_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
78910 { 25202 /* v_or_b32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
79193 { 25619 /* v_rcp_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
79194 { 25619 /* v_rcp_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
79195 { 25619 /* v_rcp_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
79196 { 25619 /* v_rcp_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
79197 { 25619 /* v_rcp_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
79241 { 25639 /* v_rcp_iflag_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
79242 { 25639 /* v_rcp_iflag_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
79243 { 25639 /* v_rcp_iflag_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
79244 { 25639 /* v_rcp_iflag_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
79245 { 25639 /* v_rcp_iflag_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
79319 { 25719 /* v_rndne_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
79320 { 25719 /* v_rndne_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
79321 { 25719 /* v_rndne_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
79322 { 25719 /* v_rndne_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
79323 { 25719 /* v_rndne_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
79409 { 25785 /* v_rsq_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
79410 { 25785 /* v_rsq_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
79411 { 25785 /* v_rsq_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
79412 { 25785 /* v_rsq_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
79413 { 25785 /* v_rsq_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
79543 { 25916 /* v_sin_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
79544 { 25916 /* v_sin_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
79545 { 25916 /* v_sin_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
79546 { 25916 /* v_sin_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
79547 { 25916 /* v_sin_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
79618 { 25937 /* v_sqrt_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
79619 { 25937 /* v_sqrt_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
79620 { 25937 /* v_sqrt_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
79621 { 25937 /* v_sqrt_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
79622 { 25937 /* v_sqrt_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
79755 { 25998 /* v_sub_f32 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
79756 { 25998 /* v_sub_f32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
79757 { 25998 /* v_sub_f32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
79758 { 25998 /* v_sub_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
79759 { 25998 /* v_sub_f32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
80002 { 26204 /* v_subrev_f32 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
80003 { 26204 /* v_subrev_f32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
80004 { 26204 /* v_subrev_f32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
80005 { 26204 /* v_subrev_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
80006 { 26204 /* v_subrev_f32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
80152 { 26326 /* v_trunc_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP_HasDPP },
80153 { 26326 /* v_trunc_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
80154 { 26326 /* v_trunc_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
80155 { 26326 /* v_trunc_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
80156 { 26326 /* v_trunc_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },
80215 { 26398 /* v_xor_b32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP_HasDPP },
80216 { 26398 /* v_xor_b32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP_HasDPP },
80217 { 26398 /* v_xor_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP_HasDPP },
80218 { 26398 /* v_xor_b32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP_HasDPP },