reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
23560 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_dpp8_w64_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPP8, MCK_ImmFI }, }, 23606 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp8_w64_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPP8, MCK_ImmFI }, }, 23854 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_dpp8_w64_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPP8, MCK_ImmFI }, }, 23884 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_dpp8_w64_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPP8, MCK_ImmFI }, }, 72852 { 13222 /* v_add_co_ci_u32 */, 32 /* 5 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave64 }, 72853 { 13222 /* v_add_co_ci_u32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus_isWave64 }, 75917 { 21959 /* v_cndmask_b32 */, 16 /* 4 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave64 }, 75918 { 21959 /* v_cndmask_b32 */, 32 /* 5 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus_isWave64 }, 79654 { 25959 /* v_sub_co_ci_u32 */, 32 /* 5 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave64 }, 79655 { 25959 /* v_sub_co_ci_u32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus_isWave64 }, 79901 { 26156 /* v_subrev_co_ci_u32 */, 32 /* 5 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus_isWave64 }, 79902 { 26156 /* v_subrev_co_ci_u32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus_isWave64 },