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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc23559 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23568 { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23571 { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23574 { 13355 /* v_add_nc_u32 */, AMDGPU::V_ADD_NC_U32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23583 { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23587 { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23590 { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23593 { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23596 { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23605 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23612 { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23615 { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23618 { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23621 { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23624 { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23627 { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23630 { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23633 { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23636 { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23639 { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23642 { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23645 { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23648 { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23651 { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23654 { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23657 { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23660 { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23663 { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23666 { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23669 { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23672 { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23683 { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23686 { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23690 { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23693 { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23696 { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23699 { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23702 { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23705 { 23122 /* v_fmac_f16 */, AMDGPU::V_FMAC_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23707 { 23133 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23710 { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23713 { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23716 { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23719 { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23722 { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23725 { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23728 { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23731 { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23734 { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23739 { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23743 { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23747 { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23750 { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23752 { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23755 { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23759 { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23763 { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23766 { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23769 { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23773 { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23777 { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23780 { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23783 { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23786 { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23789 { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23792 { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23795 { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23798 { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23801 { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23805 { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23808 { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23811 { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23814 { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23817 { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23820 { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23823 { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23826 { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23829 { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23832 { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23835 { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23839 { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23842 { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23845 { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23848 { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23853 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23862 { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23865 { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23868 { 26067 /* v_sub_nc_u32 */, AMDGPU::V_SUB_NC_U32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23883 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23892 { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23895 { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23898 { 26230 /* v_subrev_nc_u32 */, AMDGPU::V_SUBREV_NC_U32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23903 { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23906 { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23909 { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
23912 { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_dpp8_gfx10, ConvertCustom_cvtDPP8, AMFBS_HasDPP8_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPP8, MCK_ImmFI }, },
72848 { 13222 /* v_add_co_ci_u32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
72849 { 13222 /* v_add_co_ci_u32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
72903 { 13251 /* v_add_f16 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
72904 { 13251 /* v_add_f16 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
72942 { 13261 /* v_add_f32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
72943 { 13261 /* v_add_f32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
73000 { 13355 /* v_add_nc_u32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
73001 { 13355 /* v_add_nc_u32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
73078 { 13444 /* v_and_b32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
73079 { 13444 /* v_and_b32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
73123 { 13503 /* v_ashrrev_i32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
73124 { 13503 /* v_ashrrev_i32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
73152 { 13586 /* v_bfrev_b32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
73153 { 13586 /* v_bfrev_b32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
73178 { 13598 /* v_ceil_f16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
73179 { 13598 /* v_ceil_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
73214 { 13609 /* v_ceil_f32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
73215 { 13609 /* v_ceil_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
75915 { 21959 /* v_cndmask_b32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
75916 { 21959 /* v_cndmask_b32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
75970 { 21973 /* v_cos_f16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
75971 { 21973 /* v_cos_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76006 { 21983 /* v_cos_f32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76007 { 21983 /* v_cos_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76081 { 22045 /* v_cvt_f16_f32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76082 { 22045 /* v_cvt_f16_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76120 { 22059 /* v_cvt_f16_i16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76121 { 22059 /* v_cvt_f16_i16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76152 { 22073 /* v_cvt_f16_u16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76153 { 22073 /* v_cvt_f16_u16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76184 { 22087 /* v_cvt_f32_f16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76185 { 22087 /* v_cvt_f32_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76232 { 22115 /* v_cvt_f32_i32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76233 { 22115 /* v_cvt_f32_i32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76266 { 22129 /* v_cvt_f32_u32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76267 { 22129 /* v_cvt_f32_u32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76300 { 22143 /* v_cvt_f32_ubyte0 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76301 { 22143 /* v_cvt_f32_ubyte0 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76334 { 22160 /* v_cvt_f32_ubyte1 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76335 { 22160 /* v_cvt_f32_ubyte1 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76368 { 22177 /* v_cvt_f32_ubyte2 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76369 { 22177 /* v_cvt_f32_ubyte2 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76402 { 22194 /* v_cvt_f32_ubyte3 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76403 { 22194 /* v_cvt_f32_ubyte3 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76463 { 22253 /* v_cvt_flr_i32_f32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76464 { 22253 /* v_cvt_flr_i32_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76495 { 22271 /* v_cvt_i16_f16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76496 { 22271 /* v_cvt_i16_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76529 { 22285 /* v_cvt_i32_f32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76530 { 22285 /* v_cvt_i32_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76567 { 22313 /* v_cvt_norm_i16_f16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76568 { 22313 /* v_cvt_norm_i16_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76599 { 22332 /* v_cvt_norm_u16_f16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76600 { 22332 /* v_cvt_norm_u16_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76627 { 22351 /* v_cvt_off_f32_i4 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76628 { 22351 /* v_cvt_off_f32_i4 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76715 { 22543 /* v_cvt_rpi_i32_f32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76716 { 22543 /* v_cvt_rpi_i32_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76747 { 22561 /* v_cvt_u16_f16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76748 { 22561 /* v_cvt_u16_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76781 { 22575 /* v_cvt_u32_f32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76782 { 22575 /* v_cvt_u32_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
76975 { 22899 /* v_exp_f16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
76976 { 22899 /* v_exp_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77011 { 22909 /* v_exp_f32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77012 { 22909 /* v_exp_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77072 { 22936 /* v_ffbh_i32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77073 { 22936 /* v_ffbh_i32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77098 { 22947 /* v_ffbh_u32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77099 { 22947 /* v_ffbh_u32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77124 { 22958 /* v_ffbl_b32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77125 { 22958 /* v_ffbl_b32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77150 { 22969 /* v_floor_f16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77151 { 22969 /* v_floor_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77186 { 22981 /* v_floor_f32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77187 { 22981 /* v_floor_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77290 { 23122 /* v_fmac_f16 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77291 { 23122 /* v_fmac_f16 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77301 { 23133 /* v_fmac_f32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77302 { 23133 /* v_fmac_f32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77328 { 23168 /* v_fract_f16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77329 { 23168 /* v_fract_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77364 { 23180 /* v_fract_f32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77365 { 23180 /* v_fract_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77416 { 23204 /* v_frexp_exp_i16_f16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77417 { 23204 /* v_frexp_exp_i16_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77450 { 23224 /* v_frexp_exp_i32_f32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77451 { 23224 /* v_frexp_exp_i32_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77484 { 23264 /* v_frexp_mant_f16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77485 { 23264 /* v_frexp_mant_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77520 { 23281 /* v_frexp_mant_f32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77521 { 23281 /* v_frexp_mant_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77645 { 23439 /* v_ldexp_f16 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77646 { 23439 /* v_ldexp_f16 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77718 { 23501 /* v_log_f16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77719 { 23501 /* v_log_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77754 { 23511 /* v_log_f32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77755 { 23511 /* v_log_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77831 { 23603 /* v_lshlrev_b32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77832 { 23603 /* v_lshlrev_b32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77876 { 23667 /* v_lshrrev_b32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77877 { 23667 /* v_lshrrev_b32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77919 { 23705 /* v_mac_f32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77920 { 23705 /* v_mac_f32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
77947 { 23715 /* v_mac_legacy_f32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
77948 { 23715 /* v_mac_legacy_f32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78076 { 24084 /* v_max_f16 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
78077 { 24084 /* v_max_f16 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78115 { 24094 /* v_max_f32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
78116 { 24094 /* v_max_f32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78182 { 24124 /* v_max_i32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
78183 { 24124 /* v_max_i32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78230 { 24161 /* v_max_u32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
78231 { 24161 /* v_max_u32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78365 { 24775 /* v_min_f16 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
78366 { 24775 /* v_min_f16 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78404 { 24785 /* v_min_f32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
78405 { 24785 /* v_min_f32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78471 { 24815 /* v_min_i32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
78472 { 24815 /* v_min_i32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78519 { 24852 /* v_min_u32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
78520 { 24852 /* v_min_u32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78548 { 24862 /* v_mov_b32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
78549 { 24862 /* v_mov_b32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78574 { 24872 /* v_mov_fed_b32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
78575 { 24872 /* v_mov_fed_b32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78609 { 24989 /* v_mul_f16 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
78610 { 24989 /* v_mul_f16 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78648 { 24999 /* v_mul_f32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
78649 { 24999 /* v_mul_f32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78699 { 25032 /* v_mul_hi_i32_i24 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
78700 { 25032 /* v_mul_hi_i32_i24 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78728 { 25062 /* v_mul_hi_u32_u24 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
78729 { 25062 /* v_mul_hi_u32_u24 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78757 { 25079 /* v_mul_i32_i24 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
78758 { 25079 /* v_mul_i32_i24 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78786 { 25093 /* v_mul_legacy_f32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
78787 { 25093 /* v_mul_legacy_f32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78844 { 25149 /* v_mul_u32_u24 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
78845 { 25149 /* v_mul_u32_u24 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78879 { 25182 /* v_not_b32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
78880 { 25182 /* v_not_b32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
78905 { 25202 /* v_or_b32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
78906 { 25202 /* v_or_b32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79141 { 25609 /* v_rcp_f16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
79142 { 25609 /* v_rcp_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79177 { 25619 /* v_rcp_f32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
79178 { 25619 /* v_rcp_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79225 { 25639 /* v_rcp_iflag_f32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
79226 { 25639 /* v_rcp_iflag_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79267 { 25707 /* v_rndne_f16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
79268 { 25707 /* v_rndne_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79303 { 25719 /* v_rndne_f32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
79304 { 25719 /* v_rndne_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79357 { 25775 /* v_rsq_f16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
79358 { 25775 /* v_rsq_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79393 { 25785 /* v_rsq_f32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
79394 { 25785 /* v_rsq_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79456 { 25863 /* v_sat_pk_u8_i16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
79457 { 25863 /* v_sat_pk_u8_i16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79491 { 25906 /* v_sin_f16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
79492 { 25906 /* v_sin_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79527 { 25916 /* v_sin_f32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
79528 { 25916 /* v_sin_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79566 { 25926 /* v_sqrt_f16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
79567 { 25926 /* v_sqrt_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79602 { 25937 /* v_sqrt_f32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
79603 { 25937 /* v_sqrt_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79650 { 25959 /* v_sub_co_ci_u32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
79651 { 25959 /* v_sub_co_ci_u32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79705 { 25988 /* v_sub_f16 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
79706 { 25988 /* v_sub_f16 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79744 { 25998 /* v_sub_f32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
79745 { 25998 /* v_sub_f32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79793 { 26067 /* v_sub_nc_u32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
79794 { 26067 /* v_sub_nc_u32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79897 { 26156 /* v_subrev_co_ci_u32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
79898 { 26156 /* v_subrev_co_ci_u32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79952 { 26191 /* v_subrev_f16 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
79953 { 26191 /* v_subrev_f16 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
79991 { 26204 /* v_subrev_f32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
79992 { 26204 /* v_subrev_f32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
80036 { 26230 /* v_subrev_nc_u32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
80037 { 26230 /* v_subrev_nc_u32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
80100 { 26314 /* v_trunc_f16 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
80101 { 26314 /* v_trunc_f16 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
80136 { 26326 /* v_trunc_f32 */, 4 /* 2 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
80137 { 26326 /* v_trunc_f32 */, 8 /* 3 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
80184 { 26376 /* v_xnor_b32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
80185 { 26376 /* v_xnor_b32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },
80213 { 26398 /* v_xor_b32 */, 8 /* 3 */, MCK_ImmDPP8, AMFBS_HasDPP8_isGFX10Plus },
80214 { 26398 /* v_xor_b32 */, 16 /* 4 */, MCK_ImmFI, AMFBS_HasDPP8_isGFX10Plus },