reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
23563 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_dpp_w64_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, }, 23610 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp_w64_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, }, 23857 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_dpp_w64_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, }, 23887 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_dpp_w64_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave64, { MCK_VGPR_32, MCK_VCC, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, }, 72867 { 13222 /* v_add_co_ci_u32 */, 32 /* 5 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus_isWave64 }, 72868 { 13222 /* v_add_co_ci_u32 */, 64 /* 6 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus_isWave64 }, 72869 { 13222 /* v_add_co_ci_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus_isWave64 }, 72870 { 13222 /* v_add_co_ci_u32 */, 256 /* 8 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus_isWave64 }, 72871 { 13222 /* v_add_co_ci_u32 */, 512 /* 9 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus_isWave64 }, 75936 { 21959 /* v_cndmask_b32 */, 16 /* 4 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus_isWave64 }, 75937 { 21959 /* v_cndmask_b32 */, 32 /* 5 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus_isWave64 }, 75938 { 21959 /* v_cndmask_b32 */, 64 /* 6 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus_isWave64 }, 75939 { 21959 /* v_cndmask_b32 */, 128 /* 7 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus_isWave64 }, 75940 { 21959 /* v_cndmask_b32 */, 256 /* 8 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus_isWave64 }, 79669 { 25959 /* v_sub_co_ci_u32 */, 32 /* 5 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus_isWave64 }, 79670 { 25959 /* v_sub_co_ci_u32 */, 64 /* 6 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus_isWave64 }, 79671 { 25959 /* v_sub_co_ci_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus_isWave64 }, 79672 { 25959 /* v_sub_co_ci_u32 */, 256 /* 8 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus_isWave64 }, 79673 { 25959 /* v_sub_co_ci_u32 */, 512 /* 9 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus_isWave64 }, 79916 { 26156 /* v_subrev_co_ci_u32 */, 32 /* 5 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus_isWave64 }, 79917 { 26156 /* v_subrev_co_ci_u32 */, 64 /* 6 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus_isWave64 }, 79918 { 26156 /* v_subrev_co_ci_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus_isWave64 }, 79919 { 26156 /* v_subrev_co_ci_u32 */, 256 /* 8 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus_isWave64 }, 79920 { 26156 /* v_subrev_co_ci_u32 */, 512 /* 9 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus_isWave64 },