reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
23564 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_dpp_w32_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, }, 23611 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp_w32_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, }, 23858 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_dpp_w32_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, }, 23888 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_dpp_w32_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_2__Reg1_3__ImmDPPCtrl1_5__ImmRowMask1_6__ImmBankMask1_7__ImmBoundCtrl1_8__ImmFI1_9, AMFBS_HasDPP16_isGFX10Plus_isWave32, { MCK_VGPR_32, MCK_VCC_LO, MCK_VGPR_32, MCK_VGPR_32, MCK_VCC_LO, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, }, 72878 { 13222 /* v_add_co_ci_u32 */, 32 /* 5 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus_isWave32 }, 72879 { 13222 /* v_add_co_ci_u32 */, 64 /* 6 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus_isWave32 }, 72880 { 13222 /* v_add_co_ci_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus_isWave32 }, 72881 { 13222 /* v_add_co_ci_u32 */, 256 /* 8 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus_isWave32 }, 72882 { 13222 /* v_add_co_ci_u32 */, 512 /* 9 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus_isWave32 }, 75941 { 21959 /* v_cndmask_b32 */, 16 /* 4 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus_isWave32 }, 75942 { 21959 /* v_cndmask_b32 */, 32 /* 5 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus_isWave32 }, 75943 { 21959 /* v_cndmask_b32 */, 64 /* 6 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus_isWave32 }, 75944 { 21959 /* v_cndmask_b32 */, 128 /* 7 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus_isWave32 }, 75945 { 21959 /* v_cndmask_b32 */, 256 /* 8 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus_isWave32 }, 79680 { 25959 /* v_sub_co_ci_u32 */, 32 /* 5 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus_isWave32 }, 79681 { 25959 /* v_sub_co_ci_u32 */, 64 /* 6 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus_isWave32 }, 79682 { 25959 /* v_sub_co_ci_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus_isWave32 }, 79683 { 25959 /* v_sub_co_ci_u32 */, 256 /* 8 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus_isWave32 }, 79684 { 25959 /* v_sub_co_ci_u32 */, 512 /* 9 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus_isWave32 }, 79927 { 26156 /* v_subrev_co_ci_u32 */, 32 /* 5 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus_isWave32 }, 79928 { 26156 /* v_subrev_co_ci_u32 */, 64 /* 6 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus_isWave32 }, 79929 { 26156 /* v_subrev_co_ci_u32 */, 128 /* 7 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus_isWave32 }, 79930 { 26156 /* v_subrev_co_ci_u32 */, 256 /* 8 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus_isWave32 }, 79931 { 26156 /* v_subrev_co_ci_u32 */, 512 /* 9 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus_isWave32 },