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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc23562 { 13222 /* v_add_co_ci_u32 */, AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23570 { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23573 { 13261 /* v_add_f32 */, AMDGPU::V_ADD_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23575 { 13355 /* v_add_nc_u32 */, AMDGPU::V_ADD_NC_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23585 { 13444 /* v_and_b32 */, AMDGPU::V_AND_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23589 { 13503 /* v_ashrrev_i32 */, AMDGPU::V_ASHRREV_I32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23592 { 13586 /* v_bfrev_b32 */, AMDGPU::V_BFREV_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23595 { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23598 { 13609 /* v_ceil_f32 */, AMDGPU::V_CEIL_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23609 { 21959 /* v_cndmask_b32 */, AMDGPU::V_CNDMASK_B32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23614 { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23617 { 21983 /* v_cos_f32 */, AMDGPU::V_COS_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23620 { 22045 /* v_cvt_f16_f32 */, AMDGPU::V_CVT_F16_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23623 { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23626 { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23629 { 22087 /* v_cvt_f32_f16 */, AMDGPU::V_CVT_F32_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23632 { 22115 /* v_cvt_f32_i32 */, AMDGPU::V_CVT_F32_I32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23635 { 22129 /* v_cvt_f32_u32 */, AMDGPU::V_CVT_F32_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23638 { 22143 /* v_cvt_f32_ubyte0 */, AMDGPU::V_CVT_F32_UBYTE0_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23641 { 22160 /* v_cvt_f32_ubyte1 */, AMDGPU::V_CVT_F32_UBYTE1_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23644 { 22177 /* v_cvt_f32_ubyte2 */, AMDGPU::V_CVT_F32_UBYTE2_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23647 { 22194 /* v_cvt_f32_ubyte3 */, AMDGPU::V_CVT_F32_UBYTE3_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23650 { 22253 /* v_cvt_flr_i32_f32 */, AMDGPU::V_CVT_FLR_I32_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23653 { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23656 { 22285 /* v_cvt_i32_f32 */, AMDGPU::V_CVT_I32_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23659 { 22313 /* v_cvt_norm_i16_f16 */, AMDGPU::V_CVT_NORM_I16_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23662 { 22332 /* v_cvt_norm_u16_f16 */, AMDGPU::V_CVT_NORM_U16_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23665 { 22351 /* v_cvt_off_f32_i4 */, AMDGPU::V_CVT_OFF_F32_I4_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23668 { 22543 /* v_cvt_rpi_i32_f32 */, AMDGPU::V_CVT_RPI_I32_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23671 { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23674 { 22575 /* v_cvt_u32_f32 */, AMDGPU::V_CVT_U32_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23685 { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23688 { 22909 /* v_exp_f32 */, AMDGPU::V_EXP_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23692 { 22936 /* v_ffbh_i32 */, AMDGPU::V_FFBH_I32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23695 { 22947 /* v_ffbh_u32 */, AMDGPU::V_FFBH_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23698 { 22958 /* v_ffbl_b32 */, AMDGPU::V_FFBL_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23701 { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23704 { 22981 /* v_floor_f32 */, AMDGPU::V_FLOOR_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23706 { 23122 /* v_fmac_f16 */, AMDGPU::V_FMAC_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23709 { 23133 /* v_fmac_f32 */, AMDGPU::V_FMAC_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23712 { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23715 { 23180 /* v_fract_f32 */, AMDGPU::V_FRACT_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23718 { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23721 { 23224 /* v_frexp_exp_i32_f32 */, AMDGPU::V_FREXP_EXP_I32_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23724 { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23727 { 23281 /* v_frexp_mant_f32 */, AMDGPU::V_FREXP_MANT_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23730 { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23733 { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23736 { 23511 /* v_log_f32 */, AMDGPU::V_LOG_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23741 { 23603 /* v_lshlrev_b32 */, AMDGPU::V_LSHLREV_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23745 { 23667 /* v_lshrrev_b32 */, AMDGPU::V_LSHRREV_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23749 { 23705 /* v_mac_f32 */, AMDGPU::V_MAC_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23751 { 23715 /* v_mac_legacy_f32 */, AMDGPU::V_MAC_LEGACY_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23754 { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23757 { 24094 /* v_max_f32 */, AMDGPU::V_MAX_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23761 { 24124 /* v_max_i32 */, AMDGPU::V_MAX_I32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23765 { 24161 /* v_max_u32 */, AMDGPU::V_MAX_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23768 { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23771 { 24785 /* v_min_f32 */, AMDGPU::V_MIN_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23775 { 24815 /* v_min_i32 */, AMDGPU::V_MIN_I32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23779 { 24852 /* v_min_u32 */, AMDGPU::V_MIN_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23782 { 24862 /* v_mov_b32 */, AMDGPU::V_MOV_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23785 { 24872 /* v_mov_fed_b32 */, AMDGPU::V_MOV_FED_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23788 { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23791 { 24999 /* v_mul_f32 */, AMDGPU::V_MUL_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23794 { 25032 /* v_mul_hi_i32_i24 */, AMDGPU::V_MUL_HI_I32_I24_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23797 { 25062 /* v_mul_hi_u32_u24 */, AMDGPU::V_MUL_HI_U32_U24_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23800 { 25079 /* v_mul_i32_i24 */, AMDGPU::V_MUL_I32_I24_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23803 { 25093 /* v_mul_legacy_f32 */, AMDGPU::V_MUL_LEGACY_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23807 { 25149 /* v_mul_u32_u24 */, AMDGPU::V_MUL_U32_U24_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23810 { 25182 /* v_not_b32 */, AMDGPU::V_NOT_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23813 { 25202 /* v_or_b32 */, AMDGPU::V_OR_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23816 { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23819 { 25619 /* v_rcp_f32 */, AMDGPU::V_RCP_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23822 { 25639 /* v_rcp_iflag_f32 */, AMDGPU::V_RCP_IFLAG_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23825 { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23828 { 25719 /* v_rndne_f32 */, AMDGPU::V_RNDNE_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23831 { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23834 { 25785 /* v_rsq_f32 */, AMDGPU::V_RSQ_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23837 { 25863 /* v_sat_pk_u8_i16 */, AMDGPU::V_SAT_PK_U8_I16_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5__ImmFI1_6, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23841 { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23844 { 25916 /* v_sin_f32 */, AMDGPU::V_SIN_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23847 { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23850 { 25937 /* v_sqrt_f32 */, AMDGPU::V_SQRT_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23856 { 25959 /* v_sub_co_ci_u32 */, AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23864 { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23867 { 25998 /* v_sub_f32 */, AMDGPU::V_SUB_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23869 { 26067 /* v_sub_nc_u32 */, AMDGPU::V_SUB_NC_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23886 { 26156 /* v_subrev_co_ci_u32 */, AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23894 { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23897 { 26204 /* v_subrev_f32 */, AMDGPU::V_SUBREV_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23899 { 26230 /* v_subrev_nc_u32 */, AMDGPU::V_SUBREV_NC_U32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23905 { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23908 { 26326 /* v_trunc_f32 */, AMDGPU::V_TRUNC_F32_dpp_gfx10, ConvertCustom_cvtDPP, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23911 { 26376 /* v_xnor_b32 */, AMDGPU::V_XNOR_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
23914 { 26398 /* v_xor_b32 */, AMDGPU::V_XOR_B32_dpp_gfx10, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6__ImmFI1_7, AMFBS_HasDPP16_isGFX10Plus, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl, MCK_ImmFI }, },
72856 { 13222 /* v_add_co_ci_u32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
72857 { 13222 /* v_add_co_ci_u32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
72858 { 13222 /* v_add_co_ci_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
72859 { 13222 /* v_add_co_ci_u32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
72860 { 13222 /* v_add_co_ci_u32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
72922 { 13251 /* v_add_f16 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
72923 { 13251 /* v_add_f16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
72924 { 13251 /* v_add_f16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
72925 { 13251 /* v_add_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
72926 { 13251 /* v_add_f16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
72927 { 13251 /* v_add_f16 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
72964 { 13261 /* v_add_f32 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
72965 { 13261 /* v_add_f32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
72966 { 13261 /* v_add_f32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
72967 { 13261 /* v_add_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
72968 { 13261 /* v_add_f32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
72969 { 13261 /* v_add_f32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
73002 { 13355 /* v_add_nc_u32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
73003 { 13355 /* v_add_nc_u32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
73004 { 13355 /* v_add_nc_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
73005 { 13355 /* v_add_nc_u32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
73006 { 13355 /* v_add_nc_u32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
73084 { 13444 /* v_and_b32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
73085 { 13444 /* v_and_b32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
73086 { 13444 /* v_and_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
73087 { 13444 /* v_and_b32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
73088 { 13444 /* v_and_b32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
73129 { 13503 /* v_ashrrev_i32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
73130 { 13503 /* v_ashrrev_i32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
73131 { 13503 /* v_ashrrev_i32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
73132 { 13503 /* v_ashrrev_i32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
73133 { 13503 /* v_ashrrev_i32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
73173 { 13586 /* v_bfrev_b32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
73174 { 13586 /* v_bfrev_b32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
73175 { 13586 /* v_bfrev_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
73176 { 13586 /* v_bfrev_b32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
73177 { 13586 /* v_bfrev_b32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
73208 { 13598 /* v_ceil_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
73209 { 13598 /* v_ceil_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
73210 { 13598 /* v_ceil_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
73211 { 13598 /* v_ceil_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
73212 { 13598 /* v_ceil_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
73213 { 13598 /* v_ceil_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
73247 { 13609 /* v_ceil_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
73248 { 13609 /* v_ceil_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
73249 { 13609 /* v_ceil_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
73250 { 13609 /* v_ceil_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
73251 { 13609 /* v_ceil_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
73252 { 13609 /* v_ceil_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
75925 { 21959 /* v_cndmask_b32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
75926 { 21959 /* v_cndmask_b32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
75927 { 21959 /* v_cndmask_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
75928 { 21959 /* v_cndmask_b32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
75929 { 21959 /* v_cndmask_b32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76000 { 21973 /* v_cos_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
76001 { 21973 /* v_cos_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76002 { 21973 /* v_cos_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76003 { 21973 /* v_cos_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76004 { 21973 /* v_cos_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76005 { 21973 /* v_cos_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76039 { 21983 /* v_cos_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
76040 { 21983 /* v_cos_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76041 { 21983 /* v_cos_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76042 { 21983 /* v_cos_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76043 { 21983 /* v_cos_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76044 { 21983 /* v_cos_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76114 { 22045 /* v_cvt_f16_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
76115 { 22045 /* v_cvt_f16_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76116 { 22045 /* v_cvt_f16_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76117 { 22045 /* v_cvt_f16_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76118 { 22045 /* v_cvt_f16_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76119 { 22045 /* v_cvt_f16_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76135 { 22059 /* v_cvt_f16_i16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76136 { 22059 /* v_cvt_f16_i16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76137 { 22059 /* v_cvt_f16_i16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76138 { 22059 /* v_cvt_f16_i16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76139 { 22059 /* v_cvt_f16_i16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76167 { 22073 /* v_cvt_f16_u16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76168 { 22073 /* v_cvt_f16_u16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76169 { 22073 /* v_cvt_f16_u16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76170 { 22073 /* v_cvt_f16_u16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76171 { 22073 /* v_cvt_f16_u16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76217 { 22087 /* v_cvt_f32_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
76218 { 22087 /* v_cvt_f32_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76219 { 22087 /* v_cvt_f32_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76220 { 22087 /* v_cvt_f32_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76221 { 22087 /* v_cvt_f32_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76222 { 22087 /* v_cvt_f32_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76249 { 22115 /* v_cvt_f32_i32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76250 { 22115 /* v_cvt_f32_i32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76251 { 22115 /* v_cvt_f32_i32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76252 { 22115 /* v_cvt_f32_i32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76253 { 22115 /* v_cvt_f32_i32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76283 { 22129 /* v_cvt_f32_u32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76284 { 22129 /* v_cvt_f32_u32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76285 { 22129 /* v_cvt_f32_u32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76286 { 22129 /* v_cvt_f32_u32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76287 { 22129 /* v_cvt_f32_u32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76317 { 22143 /* v_cvt_f32_ubyte0 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76318 { 22143 /* v_cvt_f32_ubyte0 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76319 { 22143 /* v_cvt_f32_ubyte0 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76320 { 22143 /* v_cvt_f32_ubyte0 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76321 { 22143 /* v_cvt_f32_ubyte0 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76351 { 22160 /* v_cvt_f32_ubyte1 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76352 { 22160 /* v_cvt_f32_ubyte1 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76353 { 22160 /* v_cvt_f32_ubyte1 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76354 { 22160 /* v_cvt_f32_ubyte1 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76355 { 22160 /* v_cvt_f32_ubyte1 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76385 { 22177 /* v_cvt_f32_ubyte2 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76386 { 22177 /* v_cvt_f32_ubyte2 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76387 { 22177 /* v_cvt_f32_ubyte2 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76388 { 22177 /* v_cvt_f32_ubyte2 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76389 { 22177 /* v_cvt_f32_ubyte2 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76419 { 22194 /* v_cvt_f32_ubyte3 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76420 { 22194 /* v_cvt_f32_ubyte3 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76421 { 22194 /* v_cvt_f32_ubyte3 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76422 { 22194 /* v_cvt_f32_ubyte3 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76423 { 22194 /* v_cvt_f32_ubyte3 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76485 { 22253 /* v_cvt_flr_i32_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
76486 { 22253 /* v_cvt_flr_i32_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76487 { 22253 /* v_cvt_flr_i32_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76488 { 22253 /* v_cvt_flr_i32_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76489 { 22253 /* v_cvt_flr_i32_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76490 { 22253 /* v_cvt_flr_i32_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76517 { 22271 /* v_cvt_i16_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
76518 { 22271 /* v_cvt_i16_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76519 { 22271 /* v_cvt_i16_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76520 { 22271 /* v_cvt_i16_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76521 { 22271 /* v_cvt_i16_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76522 { 22271 /* v_cvt_i16_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76551 { 22285 /* v_cvt_i32_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
76552 { 22285 /* v_cvt_i32_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76553 { 22285 /* v_cvt_i32_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76554 { 22285 /* v_cvt_i32_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76555 { 22285 /* v_cvt_i32_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76556 { 22285 /* v_cvt_i32_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76589 { 22313 /* v_cvt_norm_i16_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
76590 { 22313 /* v_cvt_norm_i16_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76591 { 22313 /* v_cvt_norm_i16_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76592 { 22313 /* v_cvt_norm_i16_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76593 { 22313 /* v_cvt_norm_i16_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76594 { 22313 /* v_cvt_norm_i16_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76621 { 22332 /* v_cvt_norm_u16_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
76622 { 22332 /* v_cvt_norm_u16_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76623 { 22332 /* v_cvt_norm_u16_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76624 { 22332 /* v_cvt_norm_u16_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76625 { 22332 /* v_cvt_norm_u16_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76626 { 22332 /* v_cvt_norm_u16_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76644 { 22351 /* v_cvt_off_f32_i4 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76645 { 22351 /* v_cvt_off_f32_i4 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76646 { 22351 /* v_cvt_off_f32_i4 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76647 { 22351 /* v_cvt_off_f32_i4 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76648 { 22351 /* v_cvt_off_f32_i4 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76737 { 22543 /* v_cvt_rpi_i32_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
76738 { 22543 /* v_cvt_rpi_i32_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76739 { 22543 /* v_cvt_rpi_i32_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76740 { 22543 /* v_cvt_rpi_i32_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76741 { 22543 /* v_cvt_rpi_i32_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76742 { 22543 /* v_cvt_rpi_i32_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76769 { 22561 /* v_cvt_u16_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
76770 { 22561 /* v_cvt_u16_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76771 { 22561 /* v_cvt_u16_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76772 { 22561 /* v_cvt_u16_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76773 { 22561 /* v_cvt_u16_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76774 { 22561 /* v_cvt_u16_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
76803 { 22575 /* v_cvt_u32_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
76804 { 22575 /* v_cvt_u32_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
76805 { 22575 /* v_cvt_u32_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
76806 { 22575 /* v_cvt_u32_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
76807 { 22575 /* v_cvt_u32_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
76808 { 22575 /* v_cvt_u32_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77005 { 22899 /* v_exp_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
77006 { 22899 /* v_exp_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77007 { 22899 /* v_exp_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77008 { 22899 /* v_exp_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77009 { 22899 /* v_exp_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77010 { 22899 /* v_exp_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77044 { 22909 /* v_exp_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
77045 { 22909 /* v_exp_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77046 { 22909 /* v_exp_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77047 { 22909 /* v_exp_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77048 { 22909 /* v_exp_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77049 { 22909 /* v_exp_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77093 { 22936 /* v_ffbh_i32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77094 { 22936 /* v_ffbh_i32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77095 { 22936 /* v_ffbh_i32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77096 { 22936 /* v_ffbh_i32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77097 { 22936 /* v_ffbh_i32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77119 { 22947 /* v_ffbh_u32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77120 { 22947 /* v_ffbh_u32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77121 { 22947 /* v_ffbh_u32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77122 { 22947 /* v_ffbh_u32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77123 { 22947 /* v_ffbh_u32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77145 { 22958 /* v_ffbl_b32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77146 { 22958 /* v_ffbl_b32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77147 { 22958 /* v_ffbl_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77148 { 22958 /* v_ffbl_b32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77149 { 22958 /* v_ffbl_b32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77180 { 22969 /* v_floor_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
77181 { 22969 /* v_floor_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77182 { 22969 /* v_floor_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77183 { 22969 /* v_floor_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77184 { 22969 /* v_floor_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77185 { 22969 /* v_floor_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77219 { 22981 /* v_floor_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
77220 { 22981 /* v_floor_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77221 { 22981 /* v_floor_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77222 { 22981 /* v_floor_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77223 { 22981 /* v_floor_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77224 { 22981 /* v_floor_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77295 { 23122 /* v_fmac_f16 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
77296 { 23122 /* v_fmac_f16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77297 { 23122 /* v_fmac_f16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77298 { 23122 /* v_fmac_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77299 { 23122 /* v_fmac_f16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77300 { 23122 /* v_fmac_f16 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77320 { 23133 /* v_fmac_f32 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
77321 { 23133 /* v_fmac_f32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77322 { 23133 /* v_fmac_f32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77323 { 23133 /* v_fmac_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77324 { 23133 /* v_fmac_f32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77325 { 23133 /* v_fmac_f32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77358 { 23168 /* v_fract_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
77359 { 23168 /* v_fract_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77360 { 23168 /* v_fract_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77361 { 23168 /* v_fract_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77362 { 23168 /* v_fract_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77363 { 23168 /* v_fract_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77397 { 23180 /* v_fract_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
77398 { 23180 /* v_fract_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77399 { 23180 /* v_fract_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77400 { 23180 /* v_fract_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77401 { 23180 /* v_fract_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77402 { 23180 /* v_fract_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77438 { 23204 /* v_frexp_exp_i16_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
77439 { 23204 /* v_frexp_exp_i16_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77440 { 23204 /* v_frexp_exp_i16_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77441 { 23204 /* v_frexp_exp_i16_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77442 { 23204 /* v_frexp_exp_i16_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77443 { 23204 /* v_frexp_exp_i16_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77472 { 23224 /* v_frexp_exp_i32_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
77473 { 23224 /* v_frexp_exp_i32_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77474 { 23224 /* v_frexp_exp_i32_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77475 { 23224 /* v_frexp_exp_i32_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77476 { 23224 /* v_frexp_exp_i32_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77477 { 23224 /* v_frexp_exp_i32_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77514 { 23264 /* v_frexp_mant_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
77515 { 23264 /* v_frexp_mant_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77516 { 23264 /* v_frexp_mant_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77517 { 23264 /* v_frexp_mant_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77518 { 23264 /* v_frexp_mant_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77519 { 23264 /* v_frexp_mant_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77553 { 23281 /* v_frexp_mant_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
77554 { 23281 /* v_frexp_mant_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77555 { 23281 /* v_frexp_mant_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77556 { 23281 /* v_frexp_mant_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77557 { 23281 /* v_frexp_mant_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77558 { 23281 /* v_frexp_mant_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77668 { 23439 /* v_ldexp_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
77669 { 23439 /* v_ldexp_f16 */, 4 /* 2 */, MCK_VRegWithIntInputMods, AMFBS_HasDPP16_isGFX10Plus },
77670 { 23439 /* v_ldexp_f16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77671 { 23439 /* v_ldexp_f16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77672 { 23439 /* v_ldexp_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77673 { 23439 /* v_ldexp_f16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77674 { 23439 /* v_ldexp_f16 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77748 { 23501 /* v_log_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
77749 { 23501 /* v_log_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77750 { 23501 /* v_log_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77751 { 23501 /* v_log_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77752 { 23501 /* v_log_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77753 { 23501 /* v_log_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77787 { 23511 /* v_log_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
77788 { 23511 /* v_log_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77789 { 23511 /* v_log_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77790 { 23511 /* v_log_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77791 { 23511 /* v_log_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77792 { 23511 /* v_log_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77837 { 23603 /* v_lshlrev_b32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77838 { 23603 /* v_lshlrev_b32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77839 { 23603 /* v_lshlrev_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77840 { 23603 /* v_lshlrev_b32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77841 { 23603 /* v_lshlrev_b32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77882 { 23667 /* v_lshrrev_b32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77883 { 23667 /* v_lshrrev_b32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77884 { 23667 /* v_lshrrev_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77885 { 23667 /* v_lshrrev_b32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77886 { 23667 /* v_lshrrev_b32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77941 { 23705 /* v_mac_f32 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
77942 { 23705 /* v_mac_f32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77943 { 23705 /* v_mac_f32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77944 { 23705 /* v_mac_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77945 { 23705 /* v_mac_f32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77946 { 23705 /* v_mac_f32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
77955 { 23715 /* v_mac_legacy_f32 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
77956 { 23715 /* v_mac_legacy_f32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
77957 { 23715 /* v_mac_legacy_f32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
77958 { 23715 /* v_mac_legacy_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
77959 { 23715 /* v_mac_legacy_f32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
77960 { 23715 /* v_mac_legacy_f32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78095 { 24084 /* v_max_f16 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
78096 { 24084 /* v_max_f16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
78097 { 24084 /* v_max_f16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
78098 { 24084 /* v_max_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78099 { 24084 /* v_max_f16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
78100 { 24084 /* v_max_f16 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78137 { 24094 /* v_max_f32 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
78138 { 24094 /* v_max_f32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
78139 { 24094 /* v_max_f32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
78140 { 24094 /* v_max_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78141 { 24094 /* v_max_f32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
78142 { 24094 /* v_max_f32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78188 { 24124 /* v_max_i32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
78189 { 24124 /* v_max_i32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
78190 { 24124 /* v_max_i32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78191 { 24124 /* v_max_i32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
78192 { 24124 /* v_max_i32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78236 { 24161 /* v_max_u32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
78237 { 24161 /* v_max_u32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
78238 { 24161 /* v_max_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78239 { 24161 /* v_max_u32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
78240 { 24161 /* v_max_u32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78384 { 24775 /* v_min_f16 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
78385 { 24775 /* v_min_f16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
78386 { 24775 /* v_min_f16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
78387 { 24775 /* v_min_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78388 { 24775 /* v_min_f16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
78389 { 24775 /* v_min_f16 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78426 { 24785 /* v_min_f32 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
78427 { 24785 /* v_min_f32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
78428 { 24785 /* v_min_f32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
78429 { 24785 /* v_min_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78430 { 24785 /* v_min_f32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
78431 { 24785 /* v_min_f32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78477 { 24815 /* v_min_i32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
78478 { 24815 /* v_min_i32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
78479 { 24815 /* v_min_i32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78480 { 24815 /* v_min_i32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
78481 { 24815 /* v_min_i32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78525 { 24852 /* v_min_u32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
78526 { 24852 /* v_min_u32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
78527 { 24852 /* v_min_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78528 { 24852 /* v_min_u32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
78529 { 24852 /* v_min_u32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78569 { 24862 /* v_mov_b32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
78570 { 24862 /* v_mov_b32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
78571 { 24862 /* v_mov_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78572 { 24862 /* v_mov_b32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
78573 { 24862 /* v_mov_b32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78595 { 24872 /* v_mov_fed_b32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
78596 { 24872 /* v_mov_fed_b32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
78597 { 24872 /* v_mov_fed_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78598 { 24872 /* v_mov_fed_b32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
78599 { 24872 /* v_mov_fed_b32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78628 { 24989 /* v_mul_f16 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
78629 { 24989 /* v_mul_f16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
78630 { 24989 /* v_mul_f16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
78631 { 24989 /* v_mul_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78632 { 24989 /* v_mul_f16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
78633 { 24989 /* v_mul_f16 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78670 { 24999 /* v_mul_f32 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
78671 { 24999 /* v_mul_f32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
78672 { 24999 /* v_mul_f32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
78673 { 24999 /* v_mul_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78674 { 24999 /* v_mul_f32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
78675 { 24999 /* v_mul_f32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78705 { 25032 /* v_mul_hi_i32_i24 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
78706 { 25032 /* v_mul_hi_i32_i24 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
78707 { 25032 /* v_mul_hi_i32_i24 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78708 { 25032 /* v_mul_hi_i32_i24 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
78709 { 25032 /* v_mul_hi_i32_i24 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78734 { 25062 /* v_mul_hi_u32_u24 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
78735 { 25062 /* v_mul_hi_u32_u24 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
78736 { 25062 /* v_mul_hi_u32_u24 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78737 { 25062 /* v_mul_hi_u32_u24 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
78738 { 25062 /* v_mul_hi_u32_u24 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78763 { 25079 /* v_mul_i32_i24 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
78764 { 25079 /* v_mul_i32_i24 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
78765 { 25079 /* v_mul_i32_i24 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78766 { 25079 /* v_mul_i32_i24 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
78767 { 25079 /* v_mul_i32_i24 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78808 { 25093 /* v_mul_legacy_f32 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
78809 { 25093 /* v_mul_legacy_f32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
78810 { 25093 /* v_mul_legacy_f32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
78811 { 25093 /* v_mul_legacy_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78812 { 25093 /* v_mul_legacy_f32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
78813 { 25093 /* v_mul_legacy_f32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78850 { 25149 /* v_mul_u32_u24 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
78851 { 25149 /* v_mul_u32_u24 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
78852 { 25149 /* v_mul_u32_u24 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78853 { 25149 /* v_mul_u32_u24 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
78854 { 25149 /* v_mul_u32_u24 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78900 { 25182 /* v_not_b32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
78901 { 25182 /* v_not_b32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
78902 { 25182 /* v_not_b32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78903 { 25182 /* v_not_b32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
78904 { 25182 /* v_not_b32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
78911 { 25202 /* v_or_b32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
78912 { 25202 /* v_or_b32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
78913 { 25202 /* v_or_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
78914 { 25202 /* v_or_b32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
78915 { 25202 /* v_or_b32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79171 { 25609 /* v_rcp_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
79172 { 25609 /* v_rcp_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
79173 { 25609 /* v_rcp_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
79174 { 25609 /* v_rcp_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79175 { 25609 /* v_rcp_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
79176 { 25609 /* v_rcp_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79210 { 25619 /* v_rcp_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
79211 { 25619 /* v_rcp_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
79212 { 25619 /* v_rcp_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
79213 { 25619 /* v_rcp_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79214 { 25619 /* v_rcp_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
79215 { 25619 /* v_rcp_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79258 { 25639 /* v_rcp_iflag_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
79259 { 25639 /* v_rcp_iflag_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
79260 { 25639 /* v_rcp_iflag_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
79261 { 25639 /* v_rcp_iflag_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79262 { 25639 /* v_rcp_iflag_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
79263 { 25639 /* v_rcp_iflag_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79297 { 25707 /* v_rndne_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
79298 { 25707 /* v_rndne_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
79299 { 25707 /* v_rndne_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
79300 { 25707 /* v_rndne_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79301 { 25707 /* v_rndne_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
79302 { 25707 /* v_rndne_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79336 { 25719 /* v_rndne_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
79337 { 25719 /* v_rndne_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
79338 { 25719 /* v_rndne_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
79339 { 25719 /* v_rndne_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79340 { 25719 /* v_rndne_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
79341 { 25719 /* v_rndne_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79387 { 25775 /* v_rsq_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
79388 { 25775 /* v_rsq_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
79389 { 25775 /* v_rsq_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
79390 { 25775 /* v_rsq_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79391 { 25775 /* v_rsq_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
79392 { 25775 /* v_rsq_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79426 { 25785 /* v_rsq_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
79427 { 25785 /* v_rsq_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
79428 { 25785 /* v_rsq_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
79429 { 25785 /* v_rsq_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79430 { 25785 /* v_rsq_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
79431 { 25785 /* v_rsq_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79477 { 25863 /* v_sat_pk_u8_i16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
79478 { 25863 /* v_sat_pk_u8_i16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
79479 { 25863 /* v_sat_pk_u8_i16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79480 { 25863 /* v_sat_pk_u8_i16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
79481 { 25863 /* v_sat_pk_u8_i16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79521 { 25906 /* v_sin_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
79522 { 25906 /* v_sin_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
79523 { 25906 /* v_sin_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
79524 { 25906 /* v_sin_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79525 { 25906 /* v_sin_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
79526 { 25906 /* v_sin_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79560 { 25916 /* v_sin_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
79561 { 25916 /* v_sin_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
79562 { 25916 /* v_sin_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
79563 { 25916 /* v_sin_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79564 { 25916 /* v_sin_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
79565 { 25916 /* v_sin_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79596 { 25926 /* v_sqrt_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
79597 { 25926 /* v_sqrt_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
79598 { 25926 /* v_sqrt_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
79599 { 25926 /* v_sqrt_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79600 { 25926 /* v_sqrt_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
79601 { 25926 /* v_sqrt_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79635 { 25937 /* v_sqrt_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
79636 { 25937 /* v_sqrt_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
79637 { 25937 /* v_sqrt_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
79638 { 25937 /* v_sqrt_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79639 { 25937 /* v_sqrt_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
79640 { 25937 /* v_sqrt_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79658 { 25959 /* v_sub_co_ci_u32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
79659 { 25959 /* v_sub_co_ci_u32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
79660 { 25959 /* v_sub_co_ci_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79661 { 25959 /* v_sub_co_ci_u32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
79662 { 25959 /* v_sub_co_ci_u32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79724 { 25988 /* v_sub_f16 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
79725 { 25988 /* v_sub_f16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
79726 { 25988 /* v_sub_f16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
79727 { 25988 /* v_sub_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79728 { 25988 /* v_sub_f16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
79729 { 25988 /* v_sub_f16 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79766 { 25998 /* v_sub_f32 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
79767 { 25998 /* v_sub_f32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
79768 { 25998 /* v_sub_f32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
79769 { 25998 /* v_sub_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79770 { 25998 /* v_sub_f32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
79771 { 25998 /* v_sub_f32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79795 { 26067 /* v_sub_nc_u32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
79796 { 26067 /* v_sub_nc_u32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
79797 { 26067 /* v_sub_nc_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79798 { 26067 /* v_sub_nc_u32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
79799 { 26067 /* v_sub_nc_u32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79905 { 26156 /* v_subrev_co_ci_u32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
79906 { 26156 /* v_subrev_co_ci_u32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
79907 { 26156 /* v_subrev_co_ci_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79908 { 26156 /* v_subrev_co_ci_u32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
79909 { 26156 /* v_subrev_co_ci_u32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
79971 { 26191 /* v_subrev_f16 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
79972 { 26191 /* v_subrev_f16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
79973 { 26191 /* v_subrev_f16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
79974 { 26191 /* v_subrev_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
79975 { 26191 /* v_subrev_f16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
79976 { 26191 /* v_subrev_f16 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
80013 { 26204 /* v_subrev_f32 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
80014 { 26204 /* v_subrev_f32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
80015 { 26204 /* v_subrev_f32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
80016 { 26204 /* v_subrev_f32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
80017 { 26204 /* v_subrev_f32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
80018 { 26204 /* v_subrev_f32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
80038 { 26230 /* v_subrev_nc_u32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
80039 { 26230 /* v_subrev_nc_u32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
80040 { 26230 /* v_subrev_nc_u32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
80041 { 26230 /* v_subrev_nc_u32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
80042 { 26230 /* v_subrev_nc_u32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
80130 { 26314 /* v_trunc_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
80131 { 26314 /* v_trunc_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
80132 { 26314 /* v_trunc_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
80133 { 26314 /* v_trunc_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
80134 { 26314 /* v_trunc_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
80135 { 26314 /* v_trunc_f16 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
80169 { 26326 /* v_trunc_f32 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_HasDPP16_isGFX10Plus },
80170 { 26326 /* v_trunc_f32 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
80171 { 26326 /* v_trunc_f32 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
80172 { 26326 /* v_trunc_f32 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
80173 { 26326 /* v_trunc_f32 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
80174 { 26326 /* v_trunc_f32 */, 64 /* 6 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
80190 { 26376 /* v_xnor_b32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
80191 { 26376 /* v_xnor_b32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
80192 { 26376 /* v_xnor_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
80193 { 26376 /* v_xnor_b32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
80194 { 26376 /* v_xnor_b32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },
80219 { 26398 /* v_xor_b32 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_HasDPP16_isGFX10Plus },
80220 { 26398 /* v_xor_b32 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_HasDPP16_isGFX10Plus },
80221 { 26398 /* v_xor_b32 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_HasDPP16_isGFX10Plus },
80222 { 26398 /* v_xor_b32 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_HasDPP16_isGFX10Plus },
80223 { 26398 /* v_xor_b32 */, 128 /* 7 */, MCK_ImmFI, AMFBS_HasDPP16_isGFX10Plus },