reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
11103 { 18 /* buffer_atomic_add_f32 */, AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, }, 11104 { 18 /* buffer_atomic_add_f32 */, AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, }, 11105 { 18 /* buffer_atomic_add_f32 */, AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, }, 11106 { 18 /* buffer_atomic_add_f32 */, AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, }, 11501 { 393 /* buffer_atomic_pk_add_f16 */, AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFSET_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_off, MCK_SReg_128, MCK_SCSrcB32, MCK_ImmOffset, MCK_ImmSLC }, }, 11502 { 393 /* buffer_atomic_pk_add_f16 */, AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_IDXEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_ImmOffset, MCK_ImmSLC }, }, 11503 { 393 /* buffer_atomic_pk_add_f16 */, AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VGPR_32, MCK_SReg_128, MCK_SCSrcB32, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, }, 11504 { 393 /* buffer_atomic_pk_add_f16 */, AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_vi, ConvertCustom_cvtMubufAtomic, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VGPR_32, MCK_VReg_64, MCK_SReg_128, MCK_SCSrcB32, MCK_idxen, MCK_offen, MCK_ImmOffset, MCK_ImmSLC }, }, 13120 { 5010 /* global_atomic_add_f32 */, AMDGPU::GLOBAL_ATOMIC_ADD_F32_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, }, 13121 { 5010 /* global_atomic_add_f32 */, AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, }, 13234 { 5385 /* global_atomic_pk_add_f16 */, AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_vi, Convert__Reg1_0__Reg1_1__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_off, MCK_ImmFlatOffset, MCK_ImmSLC }, }, 13235 { 5385 /* global_atomic_pk_add_f16 */, AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_vi, Convert__Reg1_0__Reg1_1__Reg1_2__ImmFlatOffset1_3__ImmSLC1_4, AMFBS_HasAtomicFaddInsts_isGFX8GFX9, { MCK_VReg_64, MCK_VGPR_32, MCK_SReg_64, MCK_ImmFlatOffset, MCK_ImmSLC }, }, 24209 { 18 /* buffer_atomic_add_f32 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 24210 { 18 /* buffer_atomic_add_f32 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 24211 { 18 /* buffer_atomic_add_f32 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 24212 { 18 /* buffer_atomic_add_f32 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 24213 { 18 /* buffer_atomic_add_f32 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 24214 { 18 /* buffer_atomic_add_f32 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 24215 { 18 /* buffer_atomic_add_f32 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 24216 { 18 /* buffer_atomic_add_f32 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 25005 { 393 /* buffer_atomic_pk_add_f16 */, 16 /* 4 */, MCK_ImmOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 25006 { 393 /* buffer_atomic_pk_add_f16 */, 32 /* 5 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 25007 { 393 /* buffer_atomic_pk_add_f16 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 25008 { 393 /* buffer_atomic_pk_add_f16 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 25009 { 393 /* buffer_atomic_pk_add_f16 */, 32 /* 5 */, MCK_ImmOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 25010 { 393 /* buffer_atomic_pk_add_f16 */, 64 /* 6 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 25011 { 393 /* buffer_atomic_pk_add_f16 */, 64 /* 6 */, MCK_ImmOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 25012 { 393 /* buffer_atomic_pk_add_f16 */, 128 /* 7 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 30450 { 5010 /* global_atomic_add_f32 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 30451 { 5010 /* global_atomic_add_f32 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 30452 { 5010 /* global_atomic_add_f32 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 30453 { 5010 /* global_atomic_add_f32 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 30678 { 5385 /* global_atomic_pk_add_f16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 30679 { 5385 /* global_atomic_pk_add_f16 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 30680 { 5385 /* global_atomic_pk_add_f16 */, 8 /* 3 */, MCK_ImmFlatOffset, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 }, 30681 { 5385 /* global_atomic_pk_add_f16 */, 16 /* 4 */, MCK_ImmSLC, AMFBS_HasAtomicFaddInsts_isGFX8GFX9 },