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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc22797 { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22799 { 13368 /* v_add_u16 */, AMDGPU::V_ADD_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22805 { 13489 /* v_ashrrev_i16 */, AMDGPU::V_ASHRREV_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22808 { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22810 { 13641 /* v_cmp_class_f16 */, AMDGPU::V_CMP_CLASS_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22812 { 13749 /* v_cmp_eq_f16 */, AMDGPU::V_CMP_EQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22814 { 13839 /* v_cmp_eq_i16 */, AMDGPU::V_CMP_EQ_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22816 { 13929 /* v_cmp_eq_u16 */, AMDGPU::V_CMP_EQ_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22818 { 14019 /* v_cmp_f_f16 */, AMDGPU::V_CMP_F_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22820 { 14103 /* v_cmp_f_i16 */, AMDGPU::V_CMP_F_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22822 { 14187 /* v_cmp_f_u16 */, AMDGPU::V_CMP_F_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22824 { 14271 /* v_cmp_ge_f16 */, AMDGPU::V_CMP_GE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22826 { 14361 /* v_cmp_ge_i16 */, AMDGPU::V_CMP_GE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22828 { 14451 /* v_cmp_ge_u16 */, AMDGPU::V_CMP_GE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22830 { 14541 /* v_cmp_gt_f16 */, AMDGPU::V_CMP_GT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22832 { 14631 /* v_cmp_gt_i16 */, AMDGPU::V_CMP_GT_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22834 { 14721 /* v_cmp_gt_u16 */, AMDGPU::V_CMP_GT_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22836 { 14811 /* v_cmp_le_f16 */, AMDGPU::V_CMP_LE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22838 { 14901 /* v_cmp_le_i16 */, AMDGPU::V_CMP_LE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22840 { 14991 /* v_cmp_le_u16 */, AMDGPU::V_CMP_LE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22842 { 15081 /* v_cmp_lg_f16 */, AMDGPU::V_CMP_LG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22844 { 15171 /* v_cmp_lt_f16 */, AMDGPU::V_CMP_LT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22846 { 15261 /* v_cmp_lt_i16 */, AMDGPU::V_CMP_LT_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22848 { 15351 /* v_cmp_lt_u16 */, AMDGPU::V_CMP_LT_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22850 { 15441 /* v_cmp_ne_i16 */, AMDGPU::V_CMP_NE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22852 { 15531 /* v_cmp_ne_u16 */, AMDGPU::V_CMP_NE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22854 { 15621 /* v_cmp_neq_f16 */, AMDGPU::V_CMP_NEQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22856 { 15717 /* v_cmp_nge_f16 */, AMDGPU::V_CMP_NGE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22858 { 15813 /* v_cmp_ngt_f16 */, AMDGPU::V_CMP_NGT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22860 { 15909 /* v_cmp_nle_f16 */, AMDGPU::V_CMP_NLE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22862 { 16005 /* v_cmp_nlg_f16 */, AMDGPU::V_CMP_NLG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22864 { 16101 /* v_cmp_nlt_f16 */, AMDGPU::V_CMP_NLT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22866 { 16197 /* v_cmp_o_f16 */, AMDGPU::V_CMP_O_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22868 { 16281 /* v_cmp_t_i16 */, AMDGPU::V_CMP_T_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22870 { 16365 /* v_cmp_t_u16 */, AMDGPU::V_CMP_T_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22872 { 16449 /* v_cmp_tru_f16 */, AMDGPU::V_CMP_TRU_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22874 { 16545 /* v_cmp_u_f16 */, AMDGPU::V_CMP_U_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22876 { 18773 /* v_cmpx_class_f16 */, AMDGPU::V_CMPX_CLASS_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22878 { 18887 /* v_cmpx_eq_f16 */, AMDGPU::V_CMPX_EQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22880 { 18983 /* v_cmpx_eq_i16 */, AMDGPU::V_CMPX_EQ_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22882 { 19079 /* v_cmpx_eq_u16 */, AMDGPU::V_CMPX_EQ_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22884 { 19175 /* v_cmpx_f_f16 */, AMDGPU::V_CMPX_F_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22886 { 19265 /* v_cmpx_f_i16 */, AMDGPU::V_CMPX_F_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22888 { 19355 /* v_cmpx_f_u16 */, AMDGPU::V_CMPX_F_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22890 { 19445 /* v_cmpx_ge_f16 */, AMDGPU::V_CMPX_GE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22892 { 19541 /* v_cmpx_ge_i16 */, AMDGPU::V_CMPX_GE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22894 { 19637 /* v_cmpx_ge_u16 */, AMDGPU::V_CMPX_GE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22896 { 19733 /* v_cmpx_gt_f16 */, AMDGPU::V_CMPX_GT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22898 { 19829 /* v_cmpx_gt_i16 */, AMDGPU::V_CMPX_GT_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22900 { 19925 /* v_cmpx_gt_u16 */, AMDGPU::V_CMPX_GT_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22902 { 20021 /* v_cmpx_le_f16 */, AMDGPU::V_CMPX_LE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22904 { 20117 /* v_cmpx_le_i16 */, AMDGPU::V_CMPX_LE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22906 { 20213 /* v_cmpx_le_u16 */, AMDGPU::V_CMPX_LE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22908 { 20309 /* v_cmpx_lg_f16 */, AMDGPU::V_CMPX_LG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22910 { 20405 /* v_cmpx_lt_f16 */, AMDGPU::V_CMPX_LT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22912 { 20501 /* v_cmpx_lt_i16 */, AMDGPU::V_CMPX_LT_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22914 { 20597 /* v_cmpx_lt_u16 */, AMDGPU::V_CMPX_LT_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22916 { 20693 /* v_cmpx_ne_i16 */, AMDGPU::V_CMPX_NE_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22918 { 20789 /* v_cmpx_ne_u16 */, AMDGPU::V_CMPX_NE_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22920 { 20885 /* v_cmpx_neq_f16 */, AMDGPU::V_CMPX_NEQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22922 { 20987 /* v_cmpx_nge_f16 */, AMDGPU::V_CMPX_NGE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22924 { 21089 /* v_cmpx_ngt_f16 */, AMDGPU::V_CMPX_NGT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22926 { 21191 /* v_cmpx_nle_f16 */, AMDGPU::V_CMPX_NLE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22928 { 21293 /* v_cmpx_nlg_f16 */, AMDGPU::V_CMPX_NLG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22930 { 21395 /* v_cmpx_nlt_f16 */, AMDGPU::V_CMPX_NLT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22932 { 21497 /* v_cmpx_o_f16 */, AMDGPU::V_CMPX_O_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22934 { 21587 /* v_cmpx_t_i16 */, AMDGPU::V_CMPX_T_I16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22936 { 21677 /* v_cmpx_t_u16 */, AMDGPU::V_CMPX_T_U16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22938 { 21767 /* v_cmpx_tru_f16 */, AMDGPU::V_CMPX_TRU_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22940 { 21869 /* v_cmpx_u_f16 */, AMDGPU::V_CMPX_U_F16_sdwa_vi, ConvertCustom_cvtSdwaVOPC, AMFBS_Has16BitInsts_HasSDWA, { MCK_VCC, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22949 { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22952 { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22953 { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22962 { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22968 { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22970 { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22976 { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22979 { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22981 { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22983 { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22985 { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithInt32InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22986 { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
22989 { 23589 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22991 { 23653 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22993 { 23695 /* v_mac_f16 */, AMDGPU::V_MAC_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22995 { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22997 { 24114 /* v_max_i16 */, AMDGPU::V_MAX_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
22999 { 24151 /* v_max_u16 */, AMDGPU::V_MAX_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23001 { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23003 { 24805 /* v_min_i16 */, AMDGPU::V_MIN_I16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23005 { 24842 /* v_min_u16 */, AMDGPU::V_MIN_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23009 { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23015 { 25123 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23020 { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23023 { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23025 { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23028 { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23030 { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
23036 { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23038 { 26080 /* v_sub_u16 */, AMDGPU::V_SUB_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23050 { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23052 { 26246 /* v_subrev_u16 */, AMDGPU::V_SUBREV_U16_sdwa_vi, ConvertCustom_cvtSdwaVOP2, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithInt16InputMods, MCK_SDWAWithInt16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel, MCK_ImmSDWASrc1Sel }, },
23054 { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_sdwa_vi, ConvertCustom_cvtSdwaVOP1, AMFBS_Has16BitInsts_HasSDWA, { MCK_VGPR_32, MCK_SDWAWithFP16InputMods, MCK_ImmClampSI, MCK_ImmSDWADstSel, MCK_ImmSDWADstUnused, MCK_ImmSDWASrc0Sel }, },
72916 { 13251 /* v_add_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
72917 { 13251 /* v_add_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
72918 { 13251 /* v_add_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
72919 { 13251 /* v_add_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
72920 { 13251 /* v_add_f16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
72921 { 13251 /* v_add_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
73017 { 13368 /* v_add_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73018 { 13368 /* v_add_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73019 { 13368 /* v_add_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
73020 { 13368 /* v_add_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73021 { 13368 /* v_add_u16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73022 { 13368 /* v_add_u16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
73111 { 13489 /* v_ashrrev_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73112 { 13489 /* v_ashrrev_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73113 { 13489 /* v_ashrrev_i16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
73114 { 13489 /* v_ashrrev_i16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73115 { 13489 /* v_ashrrev_i16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73116 { 13489 /* v_ashrrev_i16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
73186 { 13598 /* v_ceil_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73187 { 13598 /* v_ceil_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73188 { 13598 /* v_ceil_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
73189 { 13598 /* v_ceil_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73190 { 13598 /* v_ceil_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
73276 { 13641 /* v_cmp_class_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73277 { 13641 /* v_cmp_class_f16 */, 4 /* 2 */, MCK_SDWAWithInt32InputMods, AMFBS_Has16BitInsts_HasSDWA },
73278 { 13641 /* v_cmp_class_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73279 { 13641 /* v_cmp_class_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73280 { 13641 /* v_cmp_class_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73322 { 13749 /* v_cmp_eq_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73323 { 13749 /* v_cmp_eq_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73324 { 13749 /* v_cmp_eq_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73325 { 13749 /* v_cmp_eq_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73366 { 13839 /* v_cmp_eq_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73367 { 13839 /* v_cmp_eq_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73368 { 13839 /* v_cmp_eq_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73369 { 13839 /* v_cmp_eq_i16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73398 { 13929 /* v_cmp_eq_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73399 { 13929 /* v_cmp_eq_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73400 { 13929 /* v_cmp_eq_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73401 { 13929 /* v_cmp_eq_u16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73434 { 14019 /* v_cmp_f_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73435 { 14019 /* v_cmp_f_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73436 { 14019 /* v_cmp_f_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73437 { 14019 /* v_cmp_f_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73473 { 14103 /* v_cmp_f_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73474 { 14103 /* v_cmp_f_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73475 { 14103 /* v_cmp_f_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73476 { 14103 /* v_cmp_f_i16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73500 { 14187 /* v_cmp_f_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73501 { 14187 /* v_cmp_f_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73502 { 14187 /* v_cmp_f_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73503 { 14187 /* v_cmp_f_u16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73536 { 14271 /* v_cmp_ge_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73537 { 14271 /* v_cmp_ge_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73538 { 14271 /* v_cmp_ge_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73539 { 14271 /* v_cmp_ge_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73580 { 14361 /* v_cmp_ge_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73581 { 14361 /* v_cmp_ge_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73582 { 14361 /* v_cmp_ge_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73583 { 14361 /* v_cmp_ge_i16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73612 { 14451 /* v_cmp_ge_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73613 { 14451 /* v_cmp_ge_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73614 { 14451 /* v_cmp_ge_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73615 { 14451 /* v_cmp_ge_u16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73648 { 14541 /* v_cmp_gt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73649 { 14541 /* v_cmp_gt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73650 { 14541 /* v_cmp_gt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73651 { 14541 /* v_cmp_gt_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73692 { 14631 /* v_cmp_gt_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73693 { 14631 /* v_cmp_gt_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73694 { 14631 /* v_cmp_gt_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73695 { 14631 /* v_cmp_gt_i16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73724 { 14721 /* v_cmp_gt_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73725 { 14721 /* v_cmp_gt_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73726 { 14721 /* v_cmp_gt_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73727 { 14721 /* v_cmp_gt_u16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73760 { 14811 /* v_cmp_le_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73761 { 14811 /* v_cmp_le_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73762 { 14811 /* v_cmp_le_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73763 { 14811 /* v_cmp_le_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73804 { 14901 /* v_cmp_le_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73805 { 14901 /* v_cmp_le_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73806 { 14901 /* v_cmp_le_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73807 { 14901 /* v_cmp_le_i16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73836 { 14991 /* v_cmp_le_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73837 { 14991 /* v_cmp_le_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73838 { 14991 /* v_cmp_le_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73839 { 14991 /* v_cmp_le_u16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73872 { 15081 /* v_cmp_lg_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73873 { 15081 /* v_cmp_lg_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73874 { 15081 /* v_cmp_lg_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73875 { 15081 /* v_cmp_lg_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73920 { 15171 /* v_cmp_lt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73921 { 15171 /* v_cmp_lt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73922 { 15171 /* v_cmp_lt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73923 { 15171 /* v_cmp_lt_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73964 { 15261 /* v_cmp_lt_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73965 { 15261 /* v_cmp_lt_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73966 { 15261 /* v_cmp_lt_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73967 { 15261 /* v_cmp_lt_i16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
73996 { 15351 /* v_cmp_lt_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
73997 { 15351 /* v_cmp_lt_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
73998 { 15351 /* v_cmp_lt_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
73999 { 15351 /* v_cmp_lt_u16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
74028 { 15441 /* v_cmp_ne_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74029 { 15441 /* v_cmp_ne_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74030 { 15441 /* v_cmp_ne_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74031 { 15441 /* v_cmp_ne_i16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
74060 { 15531 /* v_cmp_ne_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74061 { 15531 /* v_cmp_ne_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74062 { 15531 /* v_cmp_ne_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74063 { 15531 /* v_cmp_ne_u16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
74096 { 15621 /* v_cmp_neq_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74097 { 15621 /* v_cmp_neq_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74098 { 15621 /* v_cmp_neq_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74099 { 15621 /* v_cmp_neq_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
74144 { 15717 /* v_cmp_nge_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74145 { 15717 /* v_cmp_nge_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74146 { 15717 /* v_cmp_nge_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74147 { 15717 /* v_cmp_nge_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
74192 { 15813 /* v_cmp_ngt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74193 { 15813 /* v_cmp_ngt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74194 { 15813 /* v_cmp_ngt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74195 { 15813 /* v_cmp_ngt_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
74240 { 15909 /* v_cmp_nle_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74241 { 15909 /* v_cmp_nle_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74242 { 15909 /* v_cmp_nle_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74243 { 15909 /* v_cmp_nle_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
74288 { 16005 /* v_cmp_nlg_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74289 { 16005 /* v_cmp_nlg_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74290 { 16005 /* v_cmp_nlg_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74291 { 16005 /* v_cmp_nlg_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
74336 { 16101 /* v_cmp_nlt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74337 { 16101 /* v_cmp_nlt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74338 { 16101 /* v_cmp_nlt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74339 { 16101 /* v_cmp_nlt_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
74384 { 16197 /* v_cmp_o_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74385 { 16197 /* v_cmp_o_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74386 { 16197 /* v_cmp_o_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74387 { 16197 /* v_cmp_o_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
74423 { 16281 /* v_cmp_t_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74424 { 16281 /* v_cmp_t_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74425 { 16281 /* v_cmp_t_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74426 { 16281 /* v_cmp_t_i16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
74450 { 16365 /* v_cmp_t_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74451 { 16365 /* v_cmp_t_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74452 { 16365 /* v_cmp_t_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74453 { 16365 /* v_cmp_t_u16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
74486 { 16449 /* v_cmp_tru_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74487 { 16449 /* v_cmp_tru_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74488 { 16449 /* v_cmp_tru_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74489 { 16449 /* v_cmp_tru_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
74534 { 16545 /* v_cmp_u_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74535 { 16545 /* v_cmp_u_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74536 { 16545 /* v_cmp_u_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74537 { 16545 /* v_cmp_u_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
74772 { 18773 /* v_cmpx_class_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74773 { 18773 /* v_cmpx_class_f16 */, 4 /* 2 */, MCK_SDWAWithInt32InputMods, AMFBS_Has16BitInsts_HasSDWA },
74774 { 18773 /* v_cmpx_class_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74775 { 18773 /* v_cmpx_class_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74776 { 18773 /* v_cmpx_class_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
74813 { 18887 /* v_cmpx_eq_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74814 { 18887 /* v_cmpx_eq_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74815 { 18887 /* v_cmpx_eq_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74816 { 18887 /* v_cmpx_eq_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
74852 { 18983 /* v_cmpx_eq_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74853 { 18983 /* v_cmpx_eq_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74854 { 18983 /* v_cmpx_eq_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74855 { 18983 /* v_cmpx_eq_i16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
74879 { 19079 /* v_cmpx_eq_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74880 { 19079 /* v_cmpx_eq_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74881 { 19079 /* v_cmpx_eq_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74882 { 19079 /* v_cmpx_eq_u16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
74910 { 19175 /* v_cmpx_f_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74911 { 19175 /* v_cmpx_f_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74912 { 19175 /* v_cmpx_f_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74913 { 19175 /* v_cmpx_f_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
74946 { 19265 /* v_cmpx_f_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74947 { 19265 /* v_cmpx_f_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74948 { 19265 /* v_cmpx_f_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74949 { 19265 /* v_cmpx_f_i16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
74970 { 19355 /* v_cmpx_f_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
74971 { 19355 /* v_cmpx_f_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
74972 { 19355 /* v_cmpx_f_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
74973 { 19355 /* v_cmpx_f_u16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75001 { 19445 /* v_cmpx_ge_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75002 { 19445 /* v_cmpx_ge_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75003 { 19445 /* v_cmpx_ge_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75004 { 19445 /* v_cmpx_ge_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75040 { 19541 /* v_cmpx_ge_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75041 { 19541 /* v_cmpx_ge_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75042 { 19541 /* v_cmpx_ge_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75043 { 19541 /* v_cmpx_ge_i16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75067 { 19637 /* v_cmpx_ge_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75068 { 19637 /* v_cmpx_ge_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75069 { 19637 /* v_cmpx_ge_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75070 { 19637 /* v_cmpx_ge_u16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75098 { 19733 /* v_cmpx_gt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75099 { 19733 /* v_cmpx_gt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75100 { 19733 /* v_cmpx_gt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75101 { 19733 /* v_cmpx_gt_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75137 { 19829 /* v_cmpx_gt_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75138 { 19829 /* v_cmpx_gt_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75139 { 19829 /* v_cmpx_gt_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75140 { 19829 /* v_cmpx_gt_i16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75164 { 19925 /* v_cmpx_gt_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75165 { 19925 /* v_cmpx_gt_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75166 { 19925 /* v_cmpx_gt_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75167 { 19925 /* v_cmpx_gt_u16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75195 { 20021 /* v_cmpx_le_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75196 { 20021 /* v_cmpx_le_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75197 { 20021 /* v_cmpx_le_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75198 { 20021 /* v_cmpx_le_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75234 { 20117 /* v_cmpx_le_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75235 { 20117 /* v_cmpx_le_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75236 { 20117 /* v_cmpx_le_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75237 { 20117 /* v_cmpx_le_i16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75261 { 20213 /* v_cmpx_le_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75262 { 20213 /* v_cmpx_le_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75263 { 20213 /* v_cmpx_le_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75264 { 20213 /* v_cmpx_le_u16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75292 { 20309 /* v_cmpx_lg_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75293 { 20309 /* v_cmpx_lg_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75294 { 20309 /* v_cmpx_lg_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75295 { 20309 /* v_cmpx_lg_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75335 { 20405 /* v_cmpx_lt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75336 { 20405 /* v_cmpx_lt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75337 { 20405 /* v_cmpx_lt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75338 { 20405 /* v_cmpx_lt_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75374 { 20501 /* v_cmpx_lt_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75375 { 20501 /* v_cmpx_lt_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75376 { 20501 /* v_cmpx_lt_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75377 { 20501 /* v_cmpx_lt_i16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75401 { 20597 /* v_cmpx_lt_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75402 { 20597 /* v_cmpx_lt_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75403 { 20597 /* v_cmpx_lt_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75404 { 20597 /* v_cmpx_lt_u16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75428 { 20693 /* v_cmpx_ne_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75429 { 20693 /* v_cmpx_ne_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75430 { 20693 /* v_cmpx_ne_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75431 { 20693 /* v_cmpx_ne_i16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75455 { 20789 /* v_cmpx_ne_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75456 { 20789 /* v_cmpx_ne_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75457 { 20789 /* v_cmpx_ne_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75458 { 20789 /* v_cmpx_ne_u16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75486 { 20885 /* v_cmpx_neq_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75487 { 20885 /* v_cmpx_neq_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75488 { 20885 /* v_cmpx_neq_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75489 { 20885 /* v_cmpx_neq_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75529 { 20987 /* v_cmpx_nge_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75530 { 20987 /* v_cmpx_nge_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75531 { 20987 /* v_cmpx_nge_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75532 { 20987 /* v_cmpx_nge_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75572 { 21089 /* v_cmpx_ngt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75573 { 21089 /* v_cmpx_ngt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75574 { 21089 /* v_cmpx_ngt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75575 { 21089 /* v_cmpx_ngt_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75615 { 21191 /* v_cmpx_nle_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75616 { 21191 /* v_cmpx_nle_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75617 { 21191 /* v_cmpx_nle_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75618 { 21191 /* v_cmpx_nle_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75658 { 21293 /* v_cmpx_nlg_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75659 { 21293 /* v_cmpx_nlg_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75660 { 21293 /* v_cmpx_nlg_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75661 { 21293 /* v_cmpx_nlg_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75701 { 21395 /* v_cmpx_nlt_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75702 { 21395 /* v_cmpx_nlt_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75703 { 21395 /* v_cmpx_nlt_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75704 { 21395 /* v_cmpx_nlt_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75744 { 21497 /* v_cmpx_o_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75745 { 21497 /* v_cmpx_o_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75746 { 21497 /* v_cmpx_o_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75747 { 21497 /* v_cmpx_o_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75780 { 21587 /* v_cmpx_t_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75781 { 21587 /* v_cmpx_t_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75782 { 21587 /* v_cmpx_t_i16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75783 { 21587 /* v_cmpx_t_i16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75804 { 21677 /* v_cmpx_t_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75805 { 21677 /* v_cmpx_t_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75806 { 21677 /* v_cmpx_t_u16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75807 { 21677 /* v_cmpx_t_u16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75835 { 21767 /* v_cmpx_tru_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75836 { 21767 /* v_cmpx_tru_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75837 { 21767 /* v_cmpx_tru_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75838 { 21767 /* v_cmpx_tru_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75878 { 21869 /* v_cmpx_u_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75879 { 21869 /* v_cmpx_u_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75880 { 21869 /* v_cmpx_u_f16 */, 16 /* 4 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75881 { 21869 /* v_cmpx_u_f16 */, 32 /* 5 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
75978 { 21973 /* v_cos_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
75979 { 21973 /* v_cos_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
75980 { 21973 /* v_cos_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
75981 { 21973 /* v_cos_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
75982 { 21973 /* v_cos_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
76130 { 22059 /* v_cvt_f16_i16 */, 2 /* 1 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
76131 { 22059 /* v_cvt_f16_i16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
76132 { 22059 /* v_cvt_f16_i16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
76133 { 22059 /* v_cvt_f16_i16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
76134 { 22059 /* v_cvt_f16_i16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
76162 { 22073 /* v_cvt_f16_u16 */, 2 /* 1 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
76163 { 22073 /* v_cvt_f16_u16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
76164 { 22073 /* v_cvt_f16_u16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
76165 { 22073 /* v_cvt_f16_u16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
76166 { 22073 /* v_cvt_f16_u16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
76497 { 22271 /* v_cvt_i16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
76498 { 22271 /* v_cvt_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
76499 { 22271 /* v_cvt_i16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
76500 { 22271 /* v_cvt_i16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
76501 { 22271 /* v_cvt_i16_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
76749 { 22561 /* v_cvt_u16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
76750 { 22561 /* v_cvt_u16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
76751 { 22561 /* v_cvt_u16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
76752 { 22561 /* v_cvt_u16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
76753 { 22561 /* v_cvt_u16_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
76983 { 22899 /* v_exp_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
76984 { 22899 /* v_exp_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
76985 { 22899 /* v_exp_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
76986 { 22899 /* v_exp_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
76987 { 22899 /* v_exp_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
77158 { 22969 /* v_floor_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
77159 { 22969 /* v_floor_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
77160 { 22969 /* v_floor_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
77161 { 22969 /* v_floor_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
77162 { 22969 /* v_floor_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
77336 { 23168 /* v_fract_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
77337 { 23168 /* v_fract_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
77338 { 23168 /* v_fract_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
77339 { 23168 /* v_fract_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
77340 { 23168 /* v_fract_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
77418 { 23204 /* v_frexp_exp_i16_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
77419 { 23204 /* v_frexp_exp_i16_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
77420 { 23204 /* v_frexp_exp_i16_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
77421 { 23204 /* v_frexp_exp_i16_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
77422 { 23204 /* v_frexp_exp_i16_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
77492 { 23264 /* v_frexp_mant_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
77493 { 23264 /* v_frexp_mant_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
77494 { 23264 /* v_frexp_mant_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
77495 { 23264 /* v_frexp_mant_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
77496 { 23264 /* v_frexp_mant_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
77661 { 23439 /* v_ldexp_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
77662 { 23439 /* v_ldexp_f16 */, 4 /* 2 */, MCK_SDWAWithInt32InputMods, AMFBS_Has16BitInsts_HasSDWA },
77663 { 23439 /* v_ldexp_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
77664 { 23439 /* v_ldexp_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
77665 { 23439 /* v_ldexp_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
77666 { 23439 /* v_ldexp_f16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
77667 { 23439 /* v_ldexp_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
77726 { 23501 /* v_log_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
77727 { 23501 /* v_log_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
77728 { 23501 /* v_log_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
77729 { 23501 /* v_log_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
77730 { 23501 /* v_log_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
77819 { 23589 /* v_lshlrev_b16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
77820 { 23589 /* v_lshlrev_b16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
77821 { 23589 /* v_lshlrev_b16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
77822 { 23589 /* v_lshlrev_b16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
77823 { 23589 /* v_lshlrev_b16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
77824 { 23589 /* v_lshlrev_b16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
77864 { 23653 /* v_lshrrev_b16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
77865 { 23653 /* v_lshrrev_b16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
77866 { 23653 /* v_lshrrev_b16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
77867 { 23653 /* v_lshrrev_b16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
77868 { 23653 /* v_lshrrev_b16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
77869 { 23653 /* v_lshrrev_b16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
77913 { 23695 /* v_mac_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
77914 { 23695 /* v_mac_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
77915 { 23695 /* v_mac_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
77916 { 23695 /* v_mac_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
77917 { 23695 /* v_mac_f16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
77918 { 23695 /* v_mac_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
78089 { 24084 /* v_max_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
78090 { 24084 /* v_max_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
78091 { 24084 /* v_max_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
78092 { 24084 /* v_max_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
78093 { 24084 /* v_max_f16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
78094 { 24084 /* v_max_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
78170 { 24114 /* v_max_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
78171 { 24114 /* v_max_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
78172 { 24114 /* v_max_i16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
78173 { 24114 /* v_max_i16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
78174 { 24114 /* v_max_i16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
78175 { 24114 /* v_max_i16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
78218 { 24151 /* v_max_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
78219 { 24151 /* v_max_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
78220 { 24151 /* v_max_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
78221 { 24151 /* v_max_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
78222 { 24151 /* v_max_u16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
78223 { 24151 /* v_max_u16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
78378 { 24775 /* v_min_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
78379 { 24775 /* v_min_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
78380 { 24775 /* v_min_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
78381 { 24775 /* v_min_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
78382 { 24775 /* v_min_f16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
78383 { 24775 /* v_min_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
78459 { 24805 /* v_min_i16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
78460 { 24805 /* v_min_i16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
78461 { 24805 /* v_min_i16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
78462 { 24805 /* v_min_i16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
78463 { 24805 /* v_min_i16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
78464 { 24805 /* v_min_i16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
78507 { 24842 /* v_min_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
78508 { 24842 /* v_min_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
78509 { 24842 /* v_min_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
78510 { 24842 /* v_min_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
78511 { 24842 /* v_min_u16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
78512 { 24842 /* v_min_u16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
78622 { 24989 /* v_mul_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
78623 { 24989 /* v_mul_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
78624 { 24989 /* v_mul_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
78625 { 24989 /* v_mul_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
78626 { 24989 /* v_mul_f16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
78627 { 24989 /* v_mul_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
78832 { 25123 /* v_mul_lo_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
78833 { 25123 /* v_mul_lo_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
78834 { 25123 /* v_mul_lo_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
78835 { 25123 /* v_mul_lo_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
78836 { 25123 /* v_mul_lo_u16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
78837 { 25123 /* v_mul_lo_u16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
79149 { 25609 /* v_rcp_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
79150 { 25609 /* v_rcp_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
79151 { 25609 /* v_rcp_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
79152 { 25609 /* v_rcp_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
79153 { 25609 /* v_rcp_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
79275 { 25707 /* v_rndne_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
79276 { 25707 /* v_rndne_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
79277 { 25707 /* v_rndne_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
79278 { 25707 /* v_rndne_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
79279 { 25707 /* v_rndne_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
79365 { 25775 /* v_rsq_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
79366 { 25775 /* v_rsq_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
79367 { 25775 /* v_rsq_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
79368 { 25775 /* v_rsq_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
79369 { 25775 /* v_rsq_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
79499 { 25906 /* v_sin_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
79500 { 25906 /* v_sin_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
79501 { 25906 /* v_sin_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
79502 { 25906 /* v_sin_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
79503 { 25906 /* v_sin_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
79574 { 25926 /* v_sqrt_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
79575 { 25926 /* v_sqrt_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
79576 { 25926 /* v_sqrt_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
79577 { 25926 /* v_sqrt_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
79578 { 25926 /* v_sqrt_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
79718 { 25988 /* v_sub_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
79719 { 25988 /* v_sub_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
79720 { 25988 /* v_sub_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
79721 { 25988 /* v_sub_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
79722 { 25988 /* v_sub_f16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
79723 { 25988 /* v_sub_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
79810 { 26080 /* v_sub_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
79811 { 26080 /* v_sub_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
79812 { 26080 /* v_sub_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
79813 { 26080 /* v_sub_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
79814 { 26080 /* v_sub_u16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
79815 { 26080 /* v_sub_u16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
79965 { 26191 /* v_subrev_f16 */, 6 /* 1, 2 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
79966 { 26191 /* v_subrev_f16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
79967 { 26191 /* v_subrev_f16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
79968 { 26191 /* v_subrev_f16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
79969 { 26191 /* v_subrev_f16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
79970 { 26191 /* v_subrev_f16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
80053 { 26246 /* v_subrev_u16 */, 6 /* 1, 2 */, MCK_SDWAWithInt16InputMods, AMFBS_Has16BitInsts_HasSDWA },
80054 { 26246 /* v_subrev_u16 */, 8 /* 3 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
80055 { 26246 /* v_subrev_u16 */, 16 /* 4 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
80056 { 26246 /* v_subrev_u16 */, 64 /* 6 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
80057 { 26246 /* v_subrev_u16 */, 128 /* 7 */, MCK_ImmSDWASrc1Sel, AMFBS_Has16BitInsts_HasSDWA },
80058 { 26246 /* v_subrev_u16 */, 32 /* 5 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },
80108 { 26314 /* v_trunc_f16 */, 2 /* 1 */, MCK_SDWAWithFP16InputMods, AMFBS_Has16BitInsts_HasSDWA },
80109 { 26314 /* v_trunc_f16 */, 4 /* 2 */, MCK_ImmClampSI, AMFBS_Has16BitInsts_HasSDWA },
80110 { 26314 /* v_trunc_f16 */, 8 /* 3 */, MCK_ImmSDWADstSel, AMFBS_Has16BitInsts_HasSDWA },
80111 { 26314 /* v_trunc_f16 */, 32 /* 5 */, MCK_ImmSDWASrc0Sel, AMFBS_Has16BitInsts_HasSDWA },
80112 { 26314 /* v_trunc_f16 */, 16 /* 4 */, MCK_ImmSDWADstUnused, AMFBS_Has16BitInsts_HasSDWA },