|
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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AMDGPU/AMDGPUGenAsmMatcher.inc23569 { 13251 /* v_add_f16 */, AMDGPU::V_ADD_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23576 { 13368 /* v_add_u16 */, AMDGPU::V_ADD_U16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23586 { 13489 /* v_ashrrev_i16 */, AMDGPU::V_ASHRREV_I16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23594 { 13598 /* v_ceil_f16 */, AMDGPU::V_CEIL_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23613 { 21973 /* v_cos_f16 */, AMDGPU::V_COS_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23622 { 22059 /* v_cvt_f16_i16 */, AMDGPU::V_CVT_F16_I16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23625 { 22073 /* v_cvt_f16_u16 */, AMDGPU::V_CVT_F16_U16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__ImmDPPCtrl1_2__ImmRowMask1_3__ImmBankMask1_4__ImmBoundCtrl1_5, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23652 { 22271 /* v_cvt_i16_f16 */, AMDGPU::V_CVT_I16_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23670 { 22561 /* v_cvt_u16_f16 */, AMDGPU::V_CVT_U16_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23684 { 22899 /* v_exp_f16 */, AMDGPU::V_EXP_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23700 { 22969 /* v_floor_f16 */, AMDGPU::V_FLOOR_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23711 { 23168 /* v_fract_f16 */, AMDGPU::V_FRACT_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23717 { 23204 /* v_frexp_exp_i16_f16 */, AMDGPU::V_FREXP_EXP_I16_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23723 { 23264 /* v_frexp_mant_f16 */, AMDGPU::V_FREXP_MANT_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23729 { 23439 /* v_ldexp_f16 */, AMDGPU::V_LDEXP_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithIntInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23732 { 23501 /* v_log_f16 */, AMDGPU::V_LOG_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23738 { 23589 /* v_lshlrev_b16 */, AMDGPU::V_LSHLREV_B16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23742 { 23653 /* v_lshrrev_b16 */, AMDGPU::V_LSHRREV_B16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23746 { 23695 /* v_mac_f16 */, AMDGPU::V_MAC_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23753 { 24084 /* v_max_f16 */, AMDGPU::V_MAX_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23758 { 24114 /* v_max_i16 */, AMDGPU::V_MAX_I16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23762 { 24151 /* v_max_u16 */, AMDGPU::V_MAX_U16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23767 { 24775 /* v_min_f16 */, AMDGPU::V_MIN_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23772 { 24805 /* v_min_i16 */, AMDGPU::V_MIN_I16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23776 { 24842 /* v_min_u16 */, AMDGPU::V_MIN_U16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23787 { 24989 /* v_mul_f16 */, AMDGPU::V_MUL_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23804 { 25123 /* v_mul_lo_u16 */, AMDGPU::V_MUL_LO_U16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23815 { 25609 /* v_rcp_f16 */, AMDGPU::V_RCP_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23824 { 25707 /* v_rndne_f16 */, AMDGPU::V_RNDNE_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23830 { 25775 /* v_rsq_f16 */, AMDGPU::V_RSQ_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23840 { 25906 /* v_sin_f16 */, AMDGPU::V_SIN_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23846 { 25926 /* v_sqrt_f16 */, AMDGPU::V_SQRT_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23863 { 25988 /* v_sub_f16 */, AMDGPU::V_SUB_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23870 { 26080 /* v_sub_u16 */, AMDGPU::V_SUB_U16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23893 { 26191 /* v_subrev_f16 */, AMDGPU::V_SUBREV_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23900 { 26246 /* v_subrev_u16 */, AMDGPU::V_SUBREV_U16_dpp_vi, Convert__Reg1_0__Tie0_1_1__Reg1_1__Reg1_2__ImmDPPCtrl1_3__ImmRowMask1_4__ImmBankMask1_5__ImmBoundCtrl1_6, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VGPR_32, MCK_VGPR_32, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
23904 { 26314 /* v_trunc_f16 */, AMDGPU::V_TRUNC_F16_dpp_vi, ConvertCustom_cvtDPP, AMFBS_Has16BitInsts_HasDPP, { MCK_VGPR_32, MCK_VRegWithFPInputMods, MCK_ImmDPPCtrl, MCK_ImmRowMask, MCK_ImmBankMask, MCK_ImmBoundCtrl }, },
72911 { 13251 /* v_add_f16 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
72912 { 13251 /* v_add_f16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
72913 { 13251 /* v_add_f16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
72914 { 13251 /* v_add_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
72915 { 13251 /* v_add_f16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
73013 { 13368 /* v_add_u16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
73014 { 13368 /* v_add_u16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
73015 { 13368 /* v_add_u16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
73016 { 13368 /* v_add_u16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
73107 { 13489 /* v_ashrrev_i16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
73108 { 13489 /* v_ashrrev_i16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
73109 { 13489 /* v_ashrrev_i16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
73110 { 13489 /* v_ashrrev_i16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
73191 { 13598 /* v_ceil_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
73192 { 13598 /* v_ceil_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
73193 { 13598 /* v_ceil_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
73194 { 13598 /* v_ceil_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
73195 { 13598 /* v_ceil_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
75983 { 21973 /* v_cos_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
75984 { 21973 /* v_cos_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
75985 { 21973 /* v_cos_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
75986 { 21973 /* v_cos_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
75987 { 21973 /* v_cos_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
76126 { 22059 /* v_cvt_f16_i16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
76127 { 22059 /* v_cvt_f16_i16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
76128 { 22059 /* v_cvt_f16_i16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
76129 { 22059 /* v_cvt_f16_i16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
76158 { 22073 /* v_cvt_f16_u16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
76159 { 22073 /* v_cvt_f16_u16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
76160 { 22073 /* v_cvt_f16_u16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
76161 { 22073 /* v_cvt_f16_u16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
76512 { 22271 /* v_cvt_i16_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
76513 { 22271 /* v_cvt_i16_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
76514 { 22271 /* v_cvt_i16_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
76515 { 22271 /* v_cvt_i16_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
76516 { 22271 /* v_cvt_i16_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
76764 { 22561 /* v_cvt_u16_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
76765 { 22561 /* v_cvt_u16_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
76766 { 22561 /* v_cvt_u16_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
76767 { 22561 /* v_cvt_u16_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
76768 { 22561 /* v_cvt_u16_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
76988 { 22899 /* v_exp_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
76989 { 22899 /* v_exp_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
76990 { 22899 /* v_exp_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
76991 { 22899 /* v_exp_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
76992 { 22899 /* v_exp_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
77163 { 22969 /* v_floor_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
77164 { 22969 /* v_floor_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
77165 { 22969 /* v_floor_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
77166 { 22969 /* v_floor_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
77167 { 22969 /* v_floor_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
77341 { 23168 /* v_fract_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
77342 { 23168 /* v_fract_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
77343 { 23168 /* v_fract_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
77344 { 23168 /* v_fract_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
77345 { 23168 /* v_fract_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
77433 { 23204 /* v_frexp_exp_i16_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
77434 { 23204 /* v_frexp_exp_i16_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
77435 { 23204 /* v_frexp_exp_i16_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
77436 { 23204 /* v_frexp_exp_i16_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
77437 { 23204 /* v_frexp_exp_i16_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
77497 { 23264 /* v_frexp_mant_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
77498 { 23264 /* v_frexp_mant_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
77499 { 23264 /* v_frexp_mant_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
77500 { 23264 /* v_frexp_mant_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
77501 { 23264 /* v_frexp_mant_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
77655 { 23439 /* v_ldexp_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
77656 { 23439 /* v_ldexp_f16 */, 4 /* 2 */, MCK_VRegWithIntInputMods, AMFBS_Has16BitInsts_HasDPP },
77657 { 23439 /* v_ldexp_f16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
77658 { 23439 /* v_ldexp_f16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
77659 { 23439 /* v_ldexp_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
77660 { 23439 /* v_ldexp_f16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
77731 { 23501 /* v_log_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
77732 { 23501 /* v_log_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
77733 { 23501 /* v_log_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
77734 { 23501 /* v_log_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
77735 { 23501 /* v_log_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
77815 { 23589 /* v_lshlrev_b16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
77816 { 23589 /* v_lshlrev_b16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
77817 { 23589 /* v_lshlrev_b16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
77818 { 23589 /* v_lshlrev_b16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
77860 { 23653 /* v_lshrrev_b16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
77861 { 23653 /* v_lshrrev_b16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
77862 { 23653 /* v_lshrrev_b16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
77863 { 23653 /* v_lshrrev_b16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
77908 { 23695 /* v_mac_f16 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
77909 { 23695 /* v_mac_f16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
77910 { 23695 /* v_mac_f16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
77911 { 23695 /* v_mac_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
77912 { 23695 /* v_mac_f16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
78084 { 24084 /* v_max_f16 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
78085 { 24084 /* v_max_f16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
78086 { 24084 /* v_max_f16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
78087 { 24084 /* v_max_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
78088 { 24084 /* v_max_f16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
78166 { 24114 /* v_max_i16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
78167 { 24114 /* v_max_i16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
78168 { 24114 /* v_max_i16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
78169 { 24114 /* v_max_i16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
78214 { 24151 /* v_max_u16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
78215 { 24151 /* v_max_u16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
78216 { 24151 /* v_max_u16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
78217 { 24151 /* v_max_u16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
78373 { 24775 /* v_min_f16 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
78374 { 24775 /* v_min_f16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
78375 { 24775 /* v_min_f16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
78376 { 24775 /* v_min_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
78377 { 24775 /* v_min_f16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
78455 { 24805 /* v_min_i16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
78456 { 24805 /* v_min_i16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
78457 { 24805 /* v_min_i16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
78458 { 24805 /* v_min_i16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
78503 { 24842 /* v_min_u16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
78504 { 24842 /* v_min_u16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
78505 { 24842 /* v_min_u16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
78506 { 24842 /* v_min_u16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
78617 { 24989 /* v_mul_f16 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
78618 { 24989 /* v_mul_f16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
78619 { 24989 /* v_mul_f16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
78620 { 24989 /* v_mul_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
78621 { 24989 /* v_mul_f16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
78828 { 25123 /* v_mul_lo_u16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
78829 { 25123 /* v_mul_lo_u16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
78830 { 25123 /* v_mul_lo_u16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
78831 { 25123 /* v_mul_lo_u16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
79154 { 25609 /* v_rcp_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
79155 { 25609 /* v_rcp_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
79156 { 25609 /* v_rcp_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
79157 { 25609 /* v_rcp_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
79158 { 25609 /* v_rcp_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
79280 { 25707 /* v_rndne_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
79281 { 25707 /* v_rndne_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
79282 { 25707 /* v_rndne_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
79283 { 25707 /* v_rndne_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
79284 { 25707 /* v_rndne_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
79370 { 25775 /* v_rsq_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
79371 { 25775 /* v_rsq_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
79372 { 25775 /* v_rsq_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
79373 { 25775 /* v_rsq_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
79374 { 25775 /* v_rsq_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
79504 { 25906 /* v_sin_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
79505 { 25906 /* v_sin_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
79506 { 25906 /* v_sin_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
79507 { 25906 /* v_sin_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
79508 { 25906 /* v_sin_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
79579 { 25926 /* v_sqrt_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
79580 { 25926 /* v_sqrt_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
79581 { 25926 /* v_sqrt_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
79582 { 25926 /* v_sqrt_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
79583 { 25926 /* v_sqrt_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
79713 { 25988 /* v_sub_f16 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
79714 { 25988 /* v_sub_f16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
79715 { 25988 /* v_sub_f16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
79716 { 25988 /* v_sub_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
79717 { 25988 /* v_sub_f16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
79806 { 26080 /* v_sub_u16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
79807 { 26080 /* v_sub_u16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
79808 { 26080 /* v_sub_u16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
79809 { 26080 /* v_sub_u16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
79960 { 26191 /* v_subrev_f16 */, 6 /* 1, 2 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
79961 { 26191 /* v_subrev_f16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
79962 { 26191 /* v_subrev_f16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
79963 { 26191 /* v_subrev_f16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
79964 { 26191 /* v_subrev_f16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
80049 { 26246 /* v_subrev_u16 */, 8 /* 3 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
80050 { 26246 /* v_subrev_u16 */, 16 /* 4 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
80051 { 26246 /* v_subrev_u16 */, 32 /* 5 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
80052 { 26246 /* v_subrev_u16 */, 64 /* 6 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },
80113 { 26314 /* v_trunc_f16 */, 2 /* 1 */, MCK_VRegWithFPInputMods, AMFBS_Has16BitInsts_HasDPP },
80114 { 26314 /* v_trunc_f16 */, 4 /* 2 */, MCK_ImmDPPCtrl, AMFBS_Has16BitInsts_HasDPP },
80115 { 26314 /* v_trunc_f16 */, 8 /* 3 */, MCK_ImmRowMask, AMFBS_Has16BitInsts_HasDPP },
80116 { 26314 /* v_trunc_f16 */, 16 /* 4 */, MCK_ImmBankMask, AMFBS_Has16BitInsts_HasDPP },
80117 { 26314 /* v_trunc_f16 */, 32 /* 5 */, MCK_ImmBoundCtrl, AMFBS_Has16BitInsts_HasDPP },