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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc12331 if ((FB[AArch64::FeatureRAS]))
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc16963 STI.getFeatureBits()[AArch64::FeatureRAS]) {
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc17679 STI.getFeatureBits()[AArch64::FeatureRAS]) {
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc15797 if ((FB[AArch64::FeatureRAS]))
gen/lib/Target/AArch64/AArch64GenSubtargetInfo.inc 261 { "ras", "Enable ARMv8 Reliability, Availability and Serviceability Extensions", AArch64::FeatureRAS, { { { 0x0ULL, 0x0ULL, 0x0ULL, } } } },
17862 if (Bits[AArch64::FeatureRAS]) HasRAS = true;
gen/lib/Target/AArch64/AArch64GenSystemOperands.inc 2354 { "ERRIDR_EL1", 0xC298, true, false, {AArch64::FeatureRAS} }, // 100
2355 { "ERXFR_EL1", 0xC2A0, true, false, {AArch64::FeatureRAS} }, // 101
2892 { "ERRSELR_EL1", 0xC299, true, true, {AArch64::FeatureRAS} }, // 638
2893 { "ERXCTLR_EL1", 0xC2A1, true, true, {AArch64::FeatureRAS} }, // 639
2894 { "ERXSTATUS_EL1", 0xC2A2, true, true, {AArch64::FeatureRAS} }, // 640
2895 { "ERXADDR_EL1", 0xC2A3, true, true, {AArch64::FeatureRAS} }, // 641
2896 { "ERXMISC0_EL1", 0xC2A8, true, true, {AArch64::FeatureRAS} }, // 642
2897 { "ERXMISC1_EL1", 0xC2A9, true, true, {AArch64::FeatureRAS} }, // 643
2898 { "DISR_EL1", 0xC609, true, true, {AArch64::FeatureRAS} }, // 644
2899 { "VDISR_EL2", 0xE609, true, true, {AArch64::FeatureRAS} }, // 645
2900 { "VSESR_EL2", 0xE293, true, true, {AArch64::FeatureRAS} }, // 646
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 2816 {"ras", {AArch64::FeatureRAS}},