reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenAsmWriter.inc
19057         MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) &&
19073         MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) &&
19180         MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) &&
19300         MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) &&
24611         MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) &&
24627         MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) &&
24734         MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) &&
24750         MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) &&
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc
19773         MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) &&
19789         MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) &&
19896         MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) &&
20016         MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) &&
25327         MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) &&
25343         MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) &&
25450         MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) &&
25466         MRI.getRegClass(AArch64::ZPR4RegClassID).contains(MI->getOperand(0).getReg()) &&
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc
 6685 static const MCOperandInfo OperandInfo284[] = { { AArch64::ZPR4RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::PPR_3bRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64commonRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, };
 6686 static const MCOperandInfo OperandInfo285[] = { { AArch64::ZPR4RegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::PPR_3bRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { AArch64::GPR64spRegClassID, 0, MCOI::OPERAND_REGISTER, 0 }, { -1, 0, MCOI::OPERAND_UNKNOWN, 0 }, };
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc
 3514   { ZPR4, ZPR4Bits, 247, 32, sizeof(ZPR4Bits), AArch64::ZPR4RegClassID, 1, true },
 7818     &AArch64MCRegisterClasses[ZPR4RegClassID],
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
 1270            MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) ||