reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc
 5301   { 8, 8, 8, VTLists+52 },    // FPR8
 5302   { 16, 16, 16, VTLists+5 },    // FPR16
 5303   { 16, 16, 16, VTLists+34 },    // PPR
 5304   { 16, 16, 16, VTLists+34 },    // PPR_3b
 5305   { 32, 32, 32, VTLists+1 },    // GPR32all
 5306   { 32, 32, 32, VTLists+0 },    // FPR32
 5307   { 32, 32, 32, VTLists+1 },    // GPR32
 5308   { 32, 32, 32, VTLists+1 },    // GPR32sp
 5309   { 32, 32, 32, VTLists+1 },    // GPR32common
 5310   { 32, 32, 32, VTLists+1 },    // GPR32arg
 5311   { 32, 32, 32, VTLists+1 },    // CCR
 5312   { 32, 32, 32, VTLists+1 },    // GPR32sponly
 5313   { 64, 64, 32, VTLists+52 },    // WSeqPairsClass
 5314   { 64, 64, 32, VTLists+52 },    // WSeqPairsClass_with_subo32_in_GPR32common
 5315   { 64, 64, 32, VTLists+52 },    // WSeqPairsClass_with_sube32_in_GPR32arg
 5316   { 64, 64, 64, VTLists+3 },    // GPR64all
 5317   { 64, 64, 64, VTLists+7 },    // FPR64
 5318   { 64, 64, 64, VTLists+3 },    // GPR64
 5319   { 64, 64, 64, VTLists+3 },    // GPR64sp
 5320   { 64, 64, 64, VTLists+3 },    // GPR64common
 5321   { 64, 64, 64, VTLists+3 },    // GPR64noip
 5322   { 64, 64, 64, VTLists+3 },    // GPR64common_and_GPR64noip
 5323   { 64, 64, 64, VTLists+3 },    // tcGPR64
 5324   { 64, 64, 64, VTLists+3 },    // GPR64noip_and_tcGPR64
 5325   { 64, 64, 64, VTLists+3 },    // GPR64arg
 5326   { 64, 64, 64, VTLists+3 },    // rtcGPR64
 5327   { 64, 64, 64, VTLists+3 },    // GPR64sponly
 5328   { 128, 128, 64, VTLists+52 },    // DD
 5329   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass
 5330   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_subo64_in_GPR64common
 5331   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_subo64_in_GPR64noip
 5332   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_sube64_in_GPR64noip
 5333   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_sube64_in_tcGPR64
 5334   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64
 5335   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_subo64_in_tcGPR64
 5336   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64
 5337   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_sub_32_in_GPR32arg
 5338   { 128, 128, 64, VTLists+52 },    // XSeqPairsClass_with_sube64_in_rtcGPR64
 5339   { 128, 128, 128, VTLists+17 },    // FPR128
 5340   { 128, 128, 128, VTLists+39 },    // ZPR
 5341   { 128, 128, 128, VTLists+26 },    // FPR128_lo
 5342   { 128, 128, 128, VTLists+39 },    // ZPR_4b
 5343   { 128, 128, 128, VTLists+39 },    // ZPR_3b
 5344   { 192, 192, 64, VTLists+52 },    // DDD
 5345   { 256, 256, 64, VTLists+52 },    // DDDD
 5346   { 256, 256, 128, VTLists+52 },    // QQ
 5347   { 256, 256, 128, VTLists+52 },    // ZPR2
 5348   { 256, 256, 128, VTLists+52 },    // QQ_with_qsub0_in_FPR128_lo
 5349   { 256, 256, 128, VTLists+52 },    // QQ_with_qsub1_in_FPR128_lo
 5350   { 256, 256, 128, VTLists+52 },    // ZPR2_with_zsub1_in_ZPR_4b
 5351   { 256, 256, 128, VTLists+52 },    // ZPR2_with_zsub_in_FPR128_lo
 5352   { 256, 256, 128, VTLists+52 },    // QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_lo
 5353   { 256, 256, 128, VTLists+52 },    // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4b
 5354   { 256, 256, 128, VTLists+52 },    // ZPR2_with_zsub0_in_ZPR_3b
 5355   { 256, 256, 128, VTLists+52 },    // ZPR2_with_zsub1_in_ZPR_3b
 5356   { 256, 256, 128, VTLists+52 },    // ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3b
 5357   { 384, 384, 128, VTLists+52 },    // QQQ
 5358   { 384, 384, 128, VTLists+52 },    // ZPR3
 5359   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub0_in_FPR128_lo
 5360   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub1_in_FPR128_lo
 5361   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub2_in_FPR128_lo
 5362   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub1_in_ZPR_4b
 5363   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub2_in_ZPR_4b
 5364   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub_in_FPR128_lo
 5365   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_lo
 5366   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
 5367   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4b
 5368   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4b
 5369   { 384, 384, 128, VTLists+52 },    // QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_lo
 5370   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4b
 5371   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub0_in_ZPR_3b
 5372   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub1_in_ZPR_3b
 5373   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub2_in_ZPR_3b
 5374   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3b
 5375   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3b
 5376   { 384, 384, 128, VTLists+52 },    // ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3b
 5377   { 512, 512, 128, VTLists+52 },    // QQQQ
 5378   { 512, 512, 128, VTLists+52 },    // ZPR4
 5379   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub0_in_FPR128_lo
 5380   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub1_in_FPR128_lo
 5381   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub2_in_FPR128_lo
 5382   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub3_in_FPR128_lo
 5383   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub1_in_ZPR_4b
 5384   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub2_in_ZPR_4b
 5385   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub3_in_ZPR_4b
 5386   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub_in_FPR128_lo
 5387   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_lo
 5388   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
 5389   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
 5390   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4b
 5391   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
 5392   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4b
 5393   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_lo
 5394   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
 5395   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4b
 5396   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4b
 5397   { 512, 512, 128, VTLists+52 },    // QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_lo
 5398   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4b
 5399   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub0_in_ZPR_3b
 5400   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub1_in_ZPR_3b
 5401   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub2_in_ZPR_3b
 5402   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub3_in_ZPR_3b
 5403   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3b
 5404   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
 5405   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3b
 5406   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3b
 5407   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3b
 5408   { 512, 512, 128, VTLists+52 },    // ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3b