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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc18751 { 5587 /* stnt1w */, AArch64::STNT1W_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
18754 { 5587 /* stnt1w */, AArch64::STNT1W_ZZR_S_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
18757 { 5587 /* stnt1w */, AArch64::STNT1W_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__Reg1_4, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
18760 { 5587 /* stnt1w */, AArch64::STNT1W_ZZR_S_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__Reg1_4, AMFBS_HasSVE2, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
26109 { 5587 /* stnt1w */, AArch64::STNT1W_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
26112 { 5587 /* stnt1w */, AArch64::STNT1W_ZZR_S_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
26115 { 5587 /* stnt1w */, AArch64::STNT1W_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__Reg1_4, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
26118 { 5587 /* stnt1w */, AArch64::STNT1W_ZZR_S_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__Reg1_4, AMFBS_HasSVE2, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc25130 case AArch64::STNT1W_ZZR_S_REAL:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc25846 case AArch64::STNT1W_ZZR_S_REAL:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 6214 case AArch64::STNT1W_ZZR_S_REAL: {