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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc18738 { 5580 /* stnt1h */, AArch64::STNT1H_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
18741 { 5580 /* stnt1h */, AArch64::STNT1H_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
18744 { 5580 /* stnt1h */, AArch64::STNT1H_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__Reg1_4, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK_GPR64, MCK__93_ }, },
18747 { 5580 /* stnt1h */, AArch64::STNT1H_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__Reg1_4, AMFBS_HasSVE2, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK_GPR64, MCK__93_ }, },
26096 { 5580 /* stnt1h */, AArch64::STNT1H_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
26099 { 5580 /* stnt1h */, AArch64::STNT1H_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
26102 { 5580 /* stnt1h */, AArch64::STNT1H_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__Reg1_4, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK_GPR64, MCK__93_ }, },
26105 { 5580 /* stnt1h */, AArch64::STNT1H_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_3__Reg1_4, AMFBS_HasSVE2, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorDReg, MCK_GPR64, MCK__93_ }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc25069 case AArch64::STNT1H_ZZR_D_REAL:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc25785 case AArch64::STNT1H_ZZR_D_REAL:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 6211 case AArch64::STNT1H_ZZR_D_REAL: