|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc18712 { 5566 /* stnt1b */, AArch64::STNT1B_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
18716 { 5566 /* stnt1b */, AArch64::STNT1B_ZZR_S_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
18718 { 5566 /* stnt1b */, AArch64::STNT1B_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__Reg1_4, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
18722 { 5566 /* stnt1b */, AArch64::STNT1B_ZZR_S_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__Reg1_4, AMFBS_HasSVE2, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
26070 { 5566 /* stnt1b */, AArch64::STNT1B_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
26074 { 5566 /* stnt1b */, AArch64::STNT1B_ZZR_S_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
26076 { 5566 /* stnt1b */, AArch64::STNT1B_ZZR_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__Reg1_4, AMFBS_HasSVE2, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
26080 { 5566 /* stnt1b */, AArch64::STNT1B_ZZR_S_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_3__Reg1_4, AMFBS_HasSVE2, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__91_, MCK_SVEVectorSReg, MCK_GPR64, MCK__93_ }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc25007 case AArch64::STNT1B_ZZR_S_REAL:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc25723 case AArch64::STNT1B_ZZR_S_REAL:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 6209 case AArch64::STNT1B_ZZR_S_REAL: