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References

gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc
17157   { 4116 /* sdiv */, AArch64::SDIVXr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
24515   { 4116 /* sdiv */, AArch64::SDIVXr, Convert__Reg1_0__Reg1_1__Reg1_2, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
gen/lib/Target/AArch64/AArch64GenDAGISel.inc
75696 /*178982*/        OPC_MorphNodeTo1, TARGET_VAL(AArch64::SDIVXr), 0,
99037 /*223160*/      OPC_MorphNodeTo1, TARGET_VAL(AArch64::SDIVXr), 0,
gen/lib/Target/AArch64/AArch64GenFastISel.inc
 7144   return fastEmitInst_rr(AArch64::SDIVXr, &AArch64::GPR64RegClass, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc
 5507       GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/AArch64::SDIVXr,
34291         GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::SDIVXr,
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc
 8691     case AArch64::SDIVXr:
lib/Target/AArch64/AArch64FastISel.cpp
 4647     DivOpc = Is64bit ? AArch64::SDIVXr : AArch64::SDIVWr;