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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 7057 { 210, 3, 1, 4, 558, 0, 0x1ULL, ImplicitList1, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #210 = ADCSXr
7059 { 212, 3, 1, 4, 863, 0, 0x1ULL, ImplicitList1, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #212 = ADCXr
7091 { 244, 3, 1, 0, 560, 0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #244 = ADDSXrr
7106 { 259, 3, 1, 0, 561, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #259 = ADDXrr
7165 { 318, 3, 1, 0, 564, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #318 = ANDSXrr
7176 { 329, 3, 1, 0, 564, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #329 = ANDXrr
7196 { 349, 3, 1, 4, 864, 0, 0x1ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #349 = ASRVXr
7249 { 402, 3, 1, 0, 566, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #402 = BICSXrr
7254 { 407, 3, 1, 0, 566, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #407 = BICXrr
7702 { 855, 3, 1, 0, 568, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #855 = EONXrr
7723 { 876, 3, 1, 0, 571, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #876 = EORXrr
9529 { 2682, 3, 1, 4, 750, 0, 0x1ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #2682 = LSLVXr
9553 { 2706, 3, 1, 4, 667, 0, 0x1ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #2706 = LSRVXr
9718 { 2871, 3, 1, 0, 573, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #2871 = ORNXrr
9728 { 2881, 3, 1, 0, 401, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #2881 = ORRXrr
9895 { 3048, 3, 1, 4, 864, 0, 0x1ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #3048 = RORVXr
10020 { 3173, 3, 1, 4, 578, 0, 0x1ULL, ImplicitList1, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #3173 = SBCSXr
10022 { 3175, 3, 1, 4, 578, 0, 0x1ULL, ImplicitList1, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #3175 = SBCXr
10063 { 3216, 3, 1, 4, 666, 0, 0x1ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #3216 = SDIVXr
10291 { 3444, 3, 1, 4, 120, 0, 0x1ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #3444 = SMULHrr
11279 { 4432, 3, 1, 0, 580, 0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #4432 = SUBSXrr
11288 { 4441, 3, 1, 0, 580, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4441 = SUBXrr
11567 { 4720, 3, 1, 4, 666, 0, 0x1ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4720 = UDIVXr
11722 { 4875, 3, 1, 4, 120, 0, 0x1ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #4875 = UMULHrr