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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 7056 { 209, 3, 1, 4, 558, 0, 0x1ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #209 = ADCSWr
7058 { 211, 3, 1, 4, 863, 0, 0x1ULL, ImplicitList1, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #211 = ADCWr
7087 { 240, 3, 1, 0, 560, 0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #240 = ADDSWrr
7102 { 255, 3, 1, 0, 560, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #255 = ADDWrr
7162 { 315, 3, 1, 0, 712, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #315 = ANDSWrr
7173 { 326, 3, 1, 0, 712, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #326 = ANDWrr
7195 { 348, 3, 1, 4, 864, 0, 0x1ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #348 = ASRVWr
7247 { 400, 3, 1, 0, 715, 0, 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #400 = BICSWrr
7252 { 405, 3, 1, 0, 715, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #405 = BICWrr
7630 { 783, 3, 1, 4, 866, 0, 0x1ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #783 = CRC32Brr
7631 { 784, 3, 1, 4, 133, 0, 0x1ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #784 = CRC32CBrr
7632 { 785, 3, 1, 4, 133, 0, 0x1ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #785 = CRC32CHrr
7633 { 786, 3, 1, 4, 133, 0, 0x1ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #786 = CRC32CWrr
7635 { 788, 3, 1, 4, 866, 0, 0x1ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #788 = CRC32Hrr
7636 { 789, 3, 1, 4, 866, 0, 0x1ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #789 = CRC32Wrr
7700 { 853, 3, 1, 0, 717, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #853 = EONWrr
7720 { 873, 3, 1, 0, 720, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #873 = EORWrr
9528 { 2681, 3, 1, 4, 750, 0, 0x1ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #2681 = LSLVWr
9552 { 2705, 3, 1, 4, 667, 0, 0x1ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #2705 = LSRVWr
9716 { 2869, 3, 1, 0, 722, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #2869 = ORNWrr
9725 { 2878, 3, 1, 0, 576, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #2878 = ORRWrr
9894 { 3047, 3, 1, 4, 864, 0, 0x1ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #3047 = RORVWr
10019 { 3172, 3, 1, 4, 578, 0, 0x1ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #3172 = SBCSWr
10021 { 3174, 3, 1, 4, 578, 0, 0x1ULL, ImplicitList1, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #3174 = SBCWr
10062 { 3215, 3, 1, 4, 665, 0, 0x1ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #3215 = SDIVWr
11275 { 4428, 3, 1, 0, 580, 0|(1ULL<<MCID::Compare), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #4428 = SUBSWrr
11284 { 4437, 3, 1, 0, 580, 0|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4437 = SUBWrr
11566 { 4719, 3, 1, 4, 665, 0, 0x1ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #4719 = UDIVWr