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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 9015 { 2168, 4, 2, 4, 53, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2168 = LD1Twov16b_POST
9019 { 2172, 4, 2, 4, 53, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2172 = LD1Twov2d_POST
9025 { 2178, 4, 2, 4, 53, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2178 = LD1Twov4s_POST
9029 { 2182, 4, 2, 4, 53, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2182 = LD1Twov8h_POST
9049 { 2202, 4, 2, 4, 61, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2202 = LD2Rv16b_POST
9053 { 2206, 4, 2, 4, 61, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2206 = LD2Rv2d_POST
9059 { 2212, 4, 2, 4, 61, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2212 = LD2Rv4s_POST
9063 { 2216, 4, 2, 4, 61, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2216 = LD2Rv8h_POST
9065 { 2218, 4, 2, 4, 157, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2218 = LD2Twov16b_POST
9067 { 2220, 4, 2, 4, 63, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2220 = LD2Twov2d_POST
9073 { 2226, 4, 2, 4, 157, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2226 = LD2Twov4s_POST
9077 { 2230, 4, 2, 4, 157, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #2230 = LD2Twov8h_POST
10996 { 4149, 4, 1, 4, 87, 0|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #4149 = ST1Twov16b_POST
11000 { 4153, 4, 1, 4, 87, 0|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #4153 = ST1Twov2d_POST
11006 { 4159, 4, 1, 4, 87, 0|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #4159 = ST1Twov4s_POST
11010 { 4163, 4, 1, 4, 87, 0|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #4163 = ST1Twov8h_POST
11033 { 4186, 4, 1, 4, 195, 0|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #4186 = ST2Twov16b_POST
11035 { 4188, 4, 1, 4, 95, 0|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #4188 = ST2Twov2d_POST
11041 { 4194, 4, 1, 4, 195, 0|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #4194 = ST2Twov4s_POST
11045 { 4198, 4, 1, 4, 195, 0|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo271, -1 ,nullptr }, // Inst #4198 = ST2Twov8h_POST