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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 9014 { 2167, 2, 1, 4, 47, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2167 = LD1Twov16b
9018 { 2171, 2, 1, 4, 47, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2171 = LD1Twov2d
9024 { 2177, 2, 1, 4, 47, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2177 = LD1Twov4s
9028 { 2181, 2, 1, 4, 47, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2181 = LD1Twov8h
9048 { 2201, 2, 1, 4, 57, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2201 = LD2Rv16b
9052 { 2205, 2, 1, 4, 57, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2205 = LD2Rv2d
9058 { 2211, 2, 1, 4, 57, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2211 = LD2Rv4s
9062 { 2215, 2, 1, 4, 57, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2215 = LD2Rv8h
9064 { 2217, 2, 1, 4, 156, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2217 = LD2Twov16b
9066 { 2219, 2, 1, 4, 59, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2219 = LD2Twov2d
9072 { 2225, 2, 1, 4, 156, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2225 = LD2Twov4s
9076 { 2229, 2, 1, 4, 156, 0|(1ULL<<MCID::MayLoad), 0x1ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #2229 = LD2Twov8h
10995 { 4148, 2, 0, 4, 82, 0|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #4148 = ST1Twov16b
10999 { 4152, 2, 0, 4, 82, 0|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #4152 = ST1Twov2d
11005 { 4158, 2, 0, 4, 82, 0|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #4158 = ST1Twov4s
11009 { 4162, 2, 0, 4, 82, 0|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #4162 = ST1Twov8h
11032 { 4185, 2, 0, 4, 194, 0|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #4185 = ST2Twov16b
11034 { 4187, 2, 0, 4, 92, 0|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #4187 = ST2Twov2d
11040 { 4193, 2, 0, 4, 194, 0|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #4193 = ST2Twov4s
11044 { 4197, 2, 0, 4, 194, 0|(1ULL<<MCID::MayStore), 0x1ULL, nullptr, nullptr, OperandInfo270, -1 ,nullptr }, // Inst #4197 = ST2Twov8h