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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 8898 { 2051, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2051 = LD1B
8899 { 2052, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2052 = LD1B_D
8901 { 2054, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2054 = LD1B_H
8904 { 2057, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2057 = LD1B_S
8906 { 2059, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2059 = LD1D
8924 { 2077, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2077 = LD1H
8925 { 2078, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2078 = LD1H_D
8928 { 2081, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2081 = LD1H_S
8954 { 2107, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2107 = LD1RQ_B
8956 { 2109, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2109 = LD1RQ_D
8958 { 2111, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2111 = LD1RQ_H
8960 { 2113, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2113 = LD1RQ_W
8986 { 2139, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2139 = LD1SB_D
8988 { 2141, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2141 = LD1SB_H
8990 { 2143, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2143 = LD1SB_S
8992 { 2145, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2145 = LD1SH_D
8994 { 2147, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2147 = LD1SH_S
8996 { 2149, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2149 = LD1SW_D
9030 { 2183, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2183 = LD1W
9031 { 2184, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2184 = LD1W_D
9295 { 2448, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2448 = LDNT1B_ZRR
9299 { 2452, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2452 = LDNT1D_ZRR
9302 { 2455, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2455 = LDNT1H_ZRR
9311 { 2464, 4, 1, 4, 0, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #2464 = LDNT1W_ZRR
10931 { 4084, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #4084 = ST1B
10932 { 4085, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #4085 = ST1B_D
10934 { 4087, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #4087 = ST1B_H
10937 { 4090, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #4090 = ST1B_S
10939 { 4092, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #4092 = ST1D
10957 { 4110, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #4110 = ST1H
10958 { 4111, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #4111 = ST1H_D
10961 { 4114, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #4114 = ST1H_S
11011 { 4164, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #4164 = ST1W
11012 { 4165, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #4165 = ST1W_D
11148 { 4301, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #4301 = STNT1B_ZRR
11152 { 4305, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #4305 = STNT1D_ZRR
11155 { 4308, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #4308 = STNT1H_ZRR
11159 { 4312, 4, 0, 4, 0, 0|(1ULL<<MCID::MayStore)|(1ULL<<MCID::UnmodeledSideEffects), 0x1ULL, nullptr, nullptr, OperandInfo256, -1 ,nullptr }, // Inst #4312 = STNT1W_ZRR