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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 8118 { 1271, 3, 1, 4, 293, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1271 = FCVTZSd
8126 { 1279, 3, 1, 4, 246, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1279 = FCVTZSv2i32_shift
8130 { 1283, 3, 1, 4, 791, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1283 = FCVTZSv4i16_shift
8153 { 1306, 3, 1, 4, 293, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1306 = FCVTZUd
8161 { 1314, 3, 1, 4, 246, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1314 = FCVTZUv2i32_shift
8165 { 1318, 3, 1, 4, 791, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #1318 = FCVTZUv4i16_shift
10044 { 3197, 3, 1, 4, 640, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3197 = SCVTFd
10052 { 3205, 3, 1, 4, 793, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3205 = SCVTFv2i32_shift
10056 { 3209, 3, 1, 4, 792, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3209 = SCVTFv4i16_shift
10112 { 3265, 3, 1, 4, 506, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3265 = SHLd
10114 { 3267, 3, 1, 4, 505, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3267 = SHLv2i32_shift
10116 { 3269, 3, 1, 4, 505, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3269 = SHLv4i16_shift
10119 { 3272, 3, 1, 4, 505, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3272 = SHLv8i8_shift
10634 { 3787, 3, 1, 4, 513, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3787 = SQSHLUd
10638 { 3791, 3, 1, 4, 513, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3791 = SQSHLUv2i32_shift
10640 { 3793, 3, 1, 4, 513, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3793 = SQSHLUv4i16_shift
10643 { 3796, 3, 1, 4, 513, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3796 = SQSHLUv8i8_shift
10653 { 3806, 3, 1, 4, 514, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3806 = SQSHLd
10663 { 3816, 3, 1, 4, 514, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3816 = SQSHLv2i32_shift
10667 { 3820, 3, 1, 4, 514, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3820 = SQSHLv4i16_shift
10673 { 3826, 3, 1, 4, 514, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3826 = SQSHLv8i8_shift
10803 { 3956, 3, 1, 4, 233, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3956 = SRSHRd
10805 { 3958, 3, 1, 4, 518, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3958 = SRSHRv2i32_shift
10807 { 3960, 3, 1, 4, 518, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3960 = SRSHRv4i16_shift
10810 { 3963, 3, 1, 4, 518, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3963 = SRSHRv8i8_shift
10843 { 3996, 3, 1, 4, 498, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3996 = SSHRd
10845 { 3998, 3, 1, 4, 497, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #3998 = SSHRv2i32_shift
10847 { 4000, 3, 1, 4, 497, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #4000 = SSHRv4i16_shift
10850 { 4003, 3, 1, 4, 497, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #4003 = SSHRv8i8_shift
11547 { 4700, 3, 1, 4, 640, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #4700 = UCVTFd
11555 { 4708, 3, 1, 4, 793, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #4708 = UCVTFv2i32_shift
11559 { 4712, 3, 1, 4, 792, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #4712 = UCVTFv4i16_shift
11857 { 5010, 3, 1, 4, 514, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #5010 = UQSHLd
11867 { 5020, 3, 1, 4, 514, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #5020 = UQSHLv2i32_shift
11871 { 5024, 3, 1, 4, 514, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #5024 = UQSHLv4i16_shift
11877 { 5030, 3, 1, 4, 514, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #5030 = UQSHLv8i8_shift
11968 { 5121, 3, 1, 4, 233, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #5121 = URSHRd
11970 { 5123, 3, 1, 4, 518, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #5123 = URSHRv2i32_shift
11972 { 5125, 3, 1, 4, 518, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #5125 = URSHRv4i16_shift
11975 { 5128, 3, 1, 4, 518, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #5128 = URSHRv8i8_shift
12011 { 5164, 3, 1, 4, 498, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #5164 = USHRd
12013 { 5166, 3, 1, 4, 497, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #5166 = USHRv2i32_shift
12015 { 5168, 3, 1, 4, 497, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #5168 = USHRv4i16_shift
12018 { 5171, 3, 1, 4, 497, 0, 0x1ULL, nullptr, nullptr, OperandInfo200, -1 ,nullptr }, // Inst #5171 = USHRv8i8_shift