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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc 7628 { 781, 3, 1, 4, 265, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #781 = CPYi64
7688 { 841, 3, 1, 4, 585, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #841 = DUPv2i32lane
7692 { 845, 3, 1, 4, 585, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #845 = DUPv4i16lane
7698 { 851, 3, 1, 4, 585, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #851 = DUPv8i8lane
9903 { 3056, 3, 1, 4, 519, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #3056 = RSHRNv2i32_shift
9904 { 3057, 3, 1, 4, 519, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #3057 = RSHRNv4i16_shift
9907 { 3060, 3, 1, 4, 519, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #3060 = RSHRNv8i8_shift
10127 { 3280, 3, 1, 4, 520, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #3280 = SHRNv2i32_shift
10128 { 3281, 3, 1, 4, 520, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #3281 = SHRNv4i16_shift
10131 { 3284, 3, 1, 4, 520, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #3284 = SHRNv8i8_shift
10605 { 3758, 3, 1, 4, 783, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #3758 = SQRSHRNv2i32_shift
10606 { 3759, 3, 1, 4, 783, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #3759 = SQRSHRNv4i16_shift
10609 { 3762, 3, 1, 4, 783, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #3762 = SQRSHRNv8i8_shift
10620 { 3773, 3, 1, 4, 783, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #3773 = SQRSHRUNv2i32_shift
10621 { 3774, 3, 1, 4, 783, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #3774 = SQRSHRUNv4i16_shift
10624 { 3777, 3, 1, 4, 783, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #3777 = SQRSHRUNv8i8_shift
10684 { 3837, 3, 1, 4, 530, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #3837 = SQSHRNv2i32_shift
10685 { 3838, 3, 1, 4, 530, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #3838 = SQSHRNv4i16_shift
10688 { 3841, 3, 1, 4, 530, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #3841 = SQSHRNv8i8_shift
10699 { 3852, 3, 1, 4, 530, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #3852 = SQSHRUNv2i32_shift
10700 { 3853, 3, 1, 4, 530, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #3853 = SQSHRUNv4i16_shift
10703 { 3856, 3, 1, 4, 530, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #3856 = SQSHRUNv8i8_shift
11839 { 4992, 3, 1, 4, 783, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #4992 = UQRSHRNv2i32_shift
11840 { 4993, 3, 1, 4, 783, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #4993 = UQRSHRNv4i16_shift
11843 { 4996, 3, 1, 4, 783, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #4996 = UQRSHRNv8i8_shift
11888 { 5041, 3, 1, 4, 530, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #5041 = UQSHRNv2i32_shift
11889 { 5042, 3, 1, 4, 530, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #5042 = UQSHRNv4i16_shift
11892 { 5045, 3, 1, 4, 530, 0, 0x1ULL, nullptr, nullptr, OperandInfo141, -1 ,nullptr }, // Inst #5045 = UQSHRNv8i8_shift