|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc16526 { 3356 /* mov */, AArch64::ORRXrs, Convert__Reg1_0__regXZR__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64 }, },
16780 { 3495 /* orr */, AArch64::ORRXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
16795 { 3495 /* orr */, AArch64::ORRXrs, Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter641_3, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_LogicalShifter64 }, },
23884 { 3356 /* mov */, AArch64::ORRXrs, Convert__Reg1_0__regXZR__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64 }, },
24138 { 3495 /* orr */, AArch64::ORRXrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64 }, },
24159 { 3495 /* orr */, AArch64::ORRXrs, Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter641_3, AMFBS_None, { MCK_GPR64, MCK_GPR64, MCK_GPR64, MCK_LogicalShifter64 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc22212 case AArch64::ORRXrs:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc22928 case AArch64::ORRXrs:
gen/lib/Target/AArch64/AArch64GenDAGISel.inc89017 /*204661*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::ORRXrs), 0,
89023 /*204674*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::ORRXrs), 0,
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 6419 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRXrs,
6433 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORRXrs,
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc18107 case AArch64::ORRXrs:
18164 case AArch64::ORRXrs:
18296 case AArch64::ORRXrs:
18393 case AArch64::ORRXrs:
29845 case AArch64::ORRXrs:
29902 case AArch64::ORRXrs:
30034 case AArch64::ORRXrs:
30131 case AArch64::ORRXrs:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc15473 case AArch64::ORRXrs:
lib/Target/AArch64/AArch64AsmPrinter.cpp 415 OutStreamer->EmitInstruction(MCInstBuilder(AArch64::ORRXrs)
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 463 case AArch64::ORRXrr: Opcode = AArch64::ORRXrs; break;
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 770 BuildMI(*MBB, &MI, DL, TII->get(AArch64::ORRXrs), ScratchReg)
785 TII->get(AArch64::ORRXrs), LdI.BaseReg)
lib/Target/AArch64/AArch64FastISel.cpp 1745 { AArch64::ORRWrs, AArch64::ORRXrs },
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 2051 case AArch64::ORRXrs:
lib/Target/AArch64/AArch64InstrInfo.cpp 1610 case AArch64::ORRXrs: // orr Xd, Xzr, Xm (LSL #0)
2625 copyGPRRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, AArch64::ORRXrs,
5665 Save = BuildMI(MF, DebugLoc(), get(AArch64::ORRXrs), Reg)
5669 Restore = BuildMI(MF, DebugLoc(), get(AArch64::ORRXrs), AArch64::LR)
5719 if (MI.getOpcode() == AArch64::ORRXrs &&
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 979 TII->get(IsStoreXReg ? AArch64::ORRXrs : AArch64::ORRWrs), LdRt)
lib/Target/AArch64/AArch64MacroFusion.cpp 312 case AArch64::ORRXrs:
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp 982 case AArch64::ORRXrs: