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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc16700 { 3414 /* mvn */, AArch64::ORNWrs, Convert__Reg1_0__regWZR__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32 }, },
16702 { 3414 /* mvn */, AArch64::ORNWrs, Convert__Reg1_0__regWZR__Reg1_1__LogicalShifter321_2, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_LogicalShifter32 }, },
16760 { 3486 /* orn */, AArch64::ORNWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
16768 { 3486 /* orn */, AArch64::ORNWrs, Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter321_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_LogicalShifter32 }, },
24058 { 3414 /* mvn */, AArch64::ORNWrs, Convert__Reg1_0__regWZR__Reg1_1__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32 }, },
24062 { 3414 /* mvn */, AArch64::ORNWrs, Convert__Reg1_0__regWZR__Reg1_1__LogicalShifter321_2, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_LogicalShifter32 }, },
24118 { 3486 /* orn */, AArch64::ORNWrs, Convert__Reg1_0__Reg1_1__Reg1_2__imm_95_0, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32 }, },
24128 { 3486 /* orn */, AArch64::ORNWrs, Convert__Reg1_0__Reg1_1__Reg1_2__LogicalShifter321_3, AMFBS_None, { MCK_GPR32, MCK_GPR32, MCK_GPR32, MCK_LogicalShifter32 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc22095 case AArch64::ORNWrs:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc22811 case AArch64::ORNWrs:
gen/lib/Target/AArch64/AArch64GenDAGISel.inc88939 /*204497*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::ORNWrs), 0,
88959 /*204546*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::ORNWrs), 0,
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 6222 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrs,
6242 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrs,
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc18104 case AArch64::ORNWrs:
18161 case AArch64::ORNWrs:
18390 case AArch64::ORNWrs:
29842 case AArch64::ORNWrs:
29899 case AArch64::ORNWrs:
30128 case AArch64::ORNWrs:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc15470 case AArch64::ORNWrs:
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 460 case AArch64::ORNWrr: Opcode = AArch64::ORNWrs; break;
lib/Target/AArch64/AArch64MacroFusion.cpp 309 case AArch64::ORNWrs:
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp 959 case AArch64::ORNWrs: