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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc88506 /*203726*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::ORNWrr), 0,
89036 /*204706*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::ORNWrr), 0,
89055 /*204748*/ OPC_MorphNodeTo1, TARGET_VAL(AArch64::ORNWrr), 0,
98761 /*222562*/ OPC_EmitNode1, TARGET_VAL(AArch64::ORNWrr), 0,
98772 /*222587*/ OPC_EmitNode1, TARGET_VAL(AArch64::ORNWrr), 0,
98783 /*222612*/ OPC_EmitNode1, TARGET_VAL(AArch64::ORNWrr), 0,
98794 /*222637*/ OPC_EmitNode1, TARGET_VAL(AArch64::ORNWrr), 0,
98805 /*222662*/ OPC_EmitNode1, TARGET_VAL(AArch64::ORNWrr), 0,
98819 /*222693*/ OPC_EmitNode1, TARGET_VAL(AArch64::ORNWrr), 0,
98830 /*222718*/ OPC_EmitNode1, TARGET_VAL(AArch64::ORNWrr), 0,
98841 /*222743*/ OPC_EmitNode1, TARGET_VAL(AArch64::ORNWrr), 0,
98852 /*222768*/ OPC_EmitNode1, TARGET_VAL(AArch64::ORNWrr), 0,
98863 /*222793*/ OPC_EmitNode1, TARGET_VAL(AArch64::ORNWrr), 0,
98877 /*222824*/ OPC_EmitNode1, TARGET_VAL(AArch64::ORNWrr), 0,
98888 /*222849*/ OPC_EmitNode1, TARGET_VAL(AArch64::ORNWrr), 0,
98899 /*222874*/ OPC_EmitNode1, TARGET_VAL(AArch64::ORNWrr), 0,
98910 /*222899*/ OPC_EmitNode1, TARGET_VAL(AArch64::ORNWrr), 0,
98921 /*222924*/ OPC_EmitNode1, TARGET_VAL(AArch64::ORNWrr), 0,
gen/lib/Target/AArch64/AArch64GenGlobalISel.inc 6309 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrr,
6329 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrr,
6860 GIR_BuildMI, /*InsnID*/0, /*Opcode*/AArch64::ORNWrr,
19136 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19162 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19188 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19214 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19240 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19266 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19292 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19318 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19344 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19370 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19396 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19422 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19448 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19474 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
19500 GIR_BuildMI, /*InsnID*/1, /*Opcode*/AArch64::ORNWrr,
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc18137 case AArch64::ORNWrr:
18188 case AArch64::ORNWrr:
29875 case AArch64::ORNWrr:
29926 case AArch64::ORNWrr:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 5466 case AArch64::ORNWrr:
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 432 case AArch64::ORNWrr:
460 case AArch64::ORNWrr: Opcode = AArch64::ORNWrs; break;
lib/Target/AArch64/AArch64InstrInfo.cpp 459 case AArch64::ORNWrr: {
746 case AArch64::ORNWrr:
lib/Target/AArch64/AArch64MacroFusion.cpp 297 case AArch64::ORNWrr: