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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc16123 { 2633 /* ldnt1w */, AArch64::LDNT1W_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
16126 { 2633 /* ldnt1w */, AArch64::LDNT1W_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
16129 { 2633 /* ldnt1w */, AArch64::LDNT1W_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_GPR64, MCK__93_ }, },
16132 { 2633 /* ldnt1w */, AArch64::LDNT1W_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_GPR64, MCK__93_ }, },
23481 { 2633 /* ldnt1w */, AArch64::LDNT1W_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
23484 { 2633 /* ldnt1w */, AArch64::LDNT1W_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__regXZR, AMFBS_HasSVE2, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
23487 { 2633 /* ldnt1w */, AArch64::LDNT1W_ZZR_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_GPR64, MCK__93_ }, },
23490 { 2633 /* ldnt1w */, AArch64::LDNT1W_ZZR_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__Reg1_6, AMFBS_HasSVE2, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_GPR64, MCK__93_ }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc20602 case AArch64::LDNT1W_ZZR_D_REAL:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc21318 case AArch64::LDNT1W_ZZR_D_REAL:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 6206 case AArch64::LDNT1W_ZZR_D_REAL: