|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc16065 { 2588 /* ldnt1b */, AArch64::LDNT1B_ZRI, Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
16066 { 2588 /* ldnt1b */, AArch64::LDNT1B_ZRI, Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList18, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
16075 { 2588 /* ldnt1b */, AArch64::LDNT1B_ZRI, Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s1, MCK_mul, MCK_vl, MCK__93_ }, },
16076 { 2588 /* ldnt1b */, AArch64::LDNT1B_ZRI, Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6, AMFBS_HasSVE, { MCK_SVEVectorList18, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s1, MCK_mul, MCK_vl, MCK__93_ }, },
23423 { 2588 /* ldnt1b */, AArch64::LDNT1B_ZRI, Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
23424 { 2588 /* ldnt1b */, AArch64::LDNT1B_ZRI, Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList18, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
23433 { 2588 /* ldnt1b */, AArch64::LDNT1B_ZRI, Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s1, MCK_mul, MCK_vl, MCK__93_ }, },
23434 { 2588 /* ldnt1b */, AArch64::LDNT1B_ZRI, Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s11_6, AMFBS_HasSVE, { MCK_SVEVectorList18, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s1, MCK_mul, MCK_vl, MCK__93_ }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc20388 case AArch64::LDNT1B_ZRI:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc21104 case AArch64::LDNT1B_ZRI:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc15316 case AArch64::LDNT1B_ZRI: