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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc15948 { 2495 /* ldff1w */, AArch64::LDFF1W_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15952 { 2495 /* ldff1w */, AArch64::LDFF1W_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15960 { 2495 /* ldff1w */, AArch64::LDFF1W_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted32, MCK__93_ }, },
15974 { 2495 /* ldff1w */, AArch64::LDFF1W_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted32, MCK__93_ }, },
23306 { 2495 /* ldff1w */, AArch64::LDFF1W_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
23310 { 2495 /* ldff1w */, AArch64::LDFF1W_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
23318 { 2495 /* ldff1w */, AArch64::LDFF1W_D_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted32, MCK__93_ }, },
23332 { 2495 /* ldff1w */, AArch64::LDFF1W_D_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted321_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted32, MCK__93_ }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc20013 case AArch64::LDFF1W_D_REAL:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc20729 case AArch64::LDFF1W_D_REAL:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc15256 case AArch64::LDFF1W_D_REAL: