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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc15821 { 2464 /* ldff1h */, AArch64::LDFF1H_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15826 { 2464 /* ldff1h */, AArch64::LDFF1H_S_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15831 { 2464 /* ldff1h */, AArch64::LDFF1H_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted16, MCK__93_ }, },
15846 { 2464 /* ldff1h */, AArch64::LDFF1H_S_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted16, MCK__93_ }, },
23179 { 2464 /* ldff1h */, AArch64::LDFF1H_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
23184 { 2464 /* ldff1h */, AArch64::LDFF1H_S_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
23189 { 2464 /* ldff1h */, AArch64::LDFF1H_S_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted16, MCK__93_ }, },
23204 { 2464 /* ldff1h */, AArch64::LDFF1H_S_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted16, MCK__93_ }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc19908 case AArch64::LDFF1H_S_REAL:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc20624 case AArch64::LDFF1H_S_REAL:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc15249 case AArch64::LDFF1H_S_REAL: