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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc15771 { 2450 /* ldff1b */, AArch64::LDFF1B_REAL, Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15772 { 2450 /* ldff1b */, AArch64::LDFF1B_REAL, Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR, AMFBS_HasSVE, { MCK_SVEVectorList18, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15788 { 2450 /* ldff1b */, AArch64::LDFF1B_REAL, Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted8, MCK__93_ }, },
15789 { 2450 /* ldff1b */, AArch64::LDFF1B_REAL, Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6, AMFBS_HasSVE, { MCK_SVEVectorList18, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted8, MCK__93_ }, },
23129 { 2450 /* ldff1b */, AArch64::LDFF1B_REAL, Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
23130 { 2450 /* ldff1b */, AArch64::LDFF1B_REAL, Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__regXZR, AMFBS_HasSVE, { MCK_SVEVectorList18, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
23146 { 2450 /* ldff1b */, AArch64::LDFF1B_REAL, Convert__SVEVectorBReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted8, MCK__93_ }, },
23147 { 2450 /* ldff1b */, AArch64::LDFF1B_REAL, Convert__SVEVectorList181_0__SVEPredicate3bAnyReg1_1__Reg1_5__GPR64shifted81_6, AMFBS_HasSVE, { MCK_SVEVectorList18, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_GPR64shifted8, MCK__93_ }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc19833 case AArch64::LDFF1B_REAL:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc20549 case AArch64::LDFF1B_REAL:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc15244 case AArch64::LDFF1B_REAL: