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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc14910 { 1854 /* ld1 */, AArch64::LD1i64_POST, Convert__Reg1_3__TypedVectorList1_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_064, MCK_IndexRange0_1, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
14911 { 1854 /* ld1 */, AArch64::LD1i64_POST, Convert__Reg1_3__TypedVectorList1_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK_TypedVectorList1_064, MCK_IndexRange0_1, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
14918 { 1854 /* ld1 */, AArch64::LD1i64_POST, Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__regXZR, AMFBS_HasNEON, { MCK__DOT_d, MCK_VecListOne128, MCK_IndexRange0_1, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
14919 { 1854 /* ld1 */, AArch64::LD1i64_POST, Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__Reg1_6, AMFBS_HasNEON, { MCK__DOT_d, MCK_VecListOne128, MCK_IndexRange0_1, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22268 { 1854 /* ld1 */, AArch64::LD1i64_POST, Convert__Reg1_3__TypedVectorList1_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_064, MCK_IndexRange0_1, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
22269 { 1854 /* ld1 */, AArch64::LD1i64_POST, Convert__Reg1_3__TypedVectorList1_0641_0__Tie1_1_1__IndexRange0_11_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK_TypedVectorList1_064, MCK_IndexRange0_1, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22276 { 1854 /* ld1 */, AArch64::LD1i64_POST, Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__regXZR, AMFBS_HasNEON, { MCK__DOT_d, MCK_VecListOne128, MCK_IndexRange0_1, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
22277 { 1854 /* ld1 */, AArch64::LD1i64_POST, Convert__Reg1_4__VecListOne1281_1__Tie1_2_2__IndexRange0_11_2__Tie0_5_5__Reg1_6, AMFBS_HasNEON, { MCK__DOT_d, MCK_VecListOne128, MCK_IndexRange0_1, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc18406 case AArch64::LD1i64_POST:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc19122 case AArch64::LD1i64_POST:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc13102 case AArch64::LD1i64_POST:
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 371 case AArch64::LD1i64_POST:
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 3889 SelectPostLoadLane(Node, 1, AArch64::LD1i64_POST);
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 357 { AArch64::LD1i64_POST, "ld1", ".d", 2, true, 8 },