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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc14834 { 1854 /* ld1 */, AArch64::LD1Twov4s_POST, Convert__Reg1_2__TypedVectorList2_4321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList2_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
14835 { 1854 /* ld1 */, AArch64::LD1Twov4s_POST, Convert__Reg1_2__TypedVectorList2_4321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList2_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
14886 { 1854 /* ld1 */, AArch64::LD1Twov4s_POST, Convert__Reg1_3__VecListTwo1281_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VecListTwo128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
14887 { 1854 /* ld1 */, AArch64::LD1Twov4s_POST, Convert__Reg1_3__VecListTwo1281_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VecListTwo128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22192 { 1854 /* ld1 */, AArch64::LD1Twov4s_POST, Convert__Reg1_2__TypedVectorList2_4321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList2_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
22193 { 1854 /* ld1 */, AArch64::LD1Twov4s_POST, Convert__Reg1_2__TypedVectorList2_4321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList2_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22244 { 1854 /* ld1 */, AArch64::LD1Twov4s_POST, Convert__Reg1_3__VecListTwo1281_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VecListTwo128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
22245 { 1854 /* ld1 */, AArch64::LD1Twov4s_POST, Convert__Reg1_3__VecListTwo1281_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VecListTwo128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc18309 case AArch64::LD1Twov4s_POST:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc19025 case AArch64::LD1Twov4s_POST:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc12739 case AArch64::LD1Twov4s_POST:
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 426 case AArch64::LD1Twov4s_POST:
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 3696 SelectPostLoad(Node, 2, AArch64::LD1Twov4s_POST, AArch64::qsub0);
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 400 { AArch64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 },