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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc14818 { 1854 /* ld1 */, AArch64::LD1Threev4s_POST, Convert__Reg1_2__TypedVectorList3_4321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList3_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_48 }, },
14819 { 1854 /* ld1 */, AArch64::LD1Threev4s_POST, Convert__Reg1_2__TypedVectorList3_4321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList3_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
14884 { 1854 /* ld1 */, AArch64::LD1Threev4s_POST, Convert__Reg1_3__VecListThree1281_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VecListThree128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_48 }, },
14885 { 1854 /* ld1 */, AArch64::LD1Threev4s_POST, Convert__Reg1_3__VecListThree1281_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VecListThree128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22176 { 1854 /* ld1 */, AArch64::LD1Threev4s_POST, Convert__Reg1_2__TypedVectorList3_4321_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList3_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_48 }, },
22177 { 1854 /* ld1 */, AArch64::LD1Threev4s_POST, Convert__Reg1_2__TypedVectorList3_4321_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList3_432, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22242 { 1854 /* ld1 */, AArch64::LD1Threev4s_POST, Convert__Reg1_3__VecListThree1281_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VecListThree128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_48 }, },
22243 { 1854 /* ld1 */, AArch64::LD1Threev4s_POST, Convert__Reg1_3__VecListThree1281_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK__DOT_4s, MCK_VecListThree128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc18205 case AArch64::LD1Threev4s_POST:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc18921 case AArch64::LD1Threev4s_POST:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc12731 case AArch64::LD1Threev4s_POST:
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 434 case AArch64::LD1Threev4s_POST:
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 3724 SelectPostLoad(Node, 3, AArch64::LD1Threev4s_POST, AArch64::qsub0);
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 416 { AArch64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 },