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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc14812 { 1854 /* ld1 */, AArch64::LD1Threev2d_POST, Convert__Reg1_2__TypedVectorList3_2641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList3_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_48 }, },
14813 { 1854 /* ld1 */, AArch64::LD1Threev2d_POST, Convert__Reg1_2__TypedVectorList3_2641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList3_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
14860 { 1854 /* ld1 */, AArch64::LD1Threev2d_POST, Convert__Reg1_3__VecListThree1281_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK__DOT_2d, MCK_VecListThree128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_48 }, },
14861 { 1854 /* ld1 */, AArch64::LD1Threev2d_POST, Convert__Reg1_3__VecListThree1281_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK__DOT_2d, MCK_VecListThree128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22170 { 1854 /* ld1 */, AArch64::LD1Threev2d_POST, Convert__Reg1_2__TypedVectorList3_2641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList3_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_48 }, },
22171 { 1854 /* ld1 */, AArch64::LD1Threev2d_POST, Convert__Reg1_2__TypedVectorList3_2641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList3_264, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22218 { 1854 /* ld1 */, AArch64::LD1Threev2d_POST, Convert__Reg1_3__VecListThree1281_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK__DOT_2d, MCK_VecListThree128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_48 }, },
22219 { 1854 /* ld1 */, AArch64::LD1Threev2d_POST, Convert__Reg1_3__VecListThree1281_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK__DOT_2d, MCK_VecListThree128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc18166 case AArch64::LD1Threev2d_POST:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc18882 case AArch64::LD1Threev2d_POST:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc12728 case AArch64::LD1Threev2d_POST:
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 433 case AArch64::LD1Threev2d_POST:
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 3730 SelectPostLoad(Node, 3, AArch64::LD1Threev2d_POST, AArch64::qsub0);
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 417 { AArch64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 },