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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc15052 { 1873 /* ld1r */, AArch64::LD1Rv1d_POST, Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
15053 { 1873 /* ld1r */, AArch64::LD1Rv1d_POST, Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
15068 { 1873 /* ld1r */, AArch64::LD1Rv1d_POST, Convert__Reg1_3__VecListOne641_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK__DOT_1d, MCK_VecListOne64, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
15069 { 1873 /* ld1r */, AArch64::LD1Rv1d_POST, Convert__Reg1_3__VecListOne641_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK__DOT_1d, MCK_VecListOne64, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22410 { 1873 /* ld1r */, AArch64::LD1Rv1d_POST, Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
22411 { 1873 /* ld1r */, AArch64::LD1Rv1d_POST, Convert__Reg1_2__TypedVectorList1_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList1_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22426 { 1873 /* ld1r */, AArch64::LD1Rv1d_POST, Convert__Reg1_3__VecListOne641_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK__DOT_1d, MCK_VecListOne64, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_8 }, },
22427 { 1873 /* ld1r */, AArch64::LD1Rv1d_POST, Convert__Reg1_3__VecListOne641_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK__DOT_1d, MCK_VecListOne64, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc17953 case AArch64::LD1Rv1d_POST:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc18669 case AArch64::LD1Rv1d_POST:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc12719 case AArch64::LD1Rv1d_POST:
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 407 case AArch64::LD1Rv1d_POST:
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 3783 SelectPostLoad(Node, 1, AArch64::LD1Rv1d_POST, AArch64::dsub0);
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 373 { AArch64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 },