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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc15132 { 1917 /* ld1rqw */, AArch64::LD1RQ_W_IMM, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15133 { 1917 /* ld1rqw */, AArch64::LD1RQ_W_IMM, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
15135 { 1917 /* ld1rqw */, AArch64::LD1RQ_W_IMM, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s16, MCK__93_ }, },
15137 { 1917 /* ld1rqw */, AArch64::LD1RQ_W_IMM, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s16, MCK__93_ }, },
22490 { 1917 /* ld1rqw */, AArch64::LD1RQ_W_IMM, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22491 { 1917 /* ld1rqw */, AArch64::LD1RQ_W_IMM, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK__93_ }, },
22493 { 1917 /* ld1rqw */, AArch64::LD1RQ_W_IMM, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s16, MCK__93_ }, },
22495 { 1917 /* ld1rqw */, AArch64::LD1RQ_W_IMM, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__Reg1_5__SImm4s161_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_GPR64sp, MCK_SImm4s16, MCK__93_ }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc17796 case AArch64::LD1RQ_W_IMM:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc18512 case AArch64::LD1RQ_W_IMM:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc15344 case AArch64::LD1RQ_W_IMM: {