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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc14786 { 1854 /* ld1 */, AArch64::LD1Fourv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
14787 { 1854 /* ld1 */, AArch64::LD1Fourv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
14896 { 1854 /* ld1 */, AArch64::LD1Fourv8h_POST, Convert__Reg1_3__VecListFour1281_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK__DOT_8h, MCK_VecListFour128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
14897 { 1854 /* ld1 */, AArch64::LD1Fourv8h_POST, Convert__Reg1_3__VecListFour1281_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK__DOT_8h, MCK_VecListFour128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22144 { 1854 /* ld1 */, AArch64::LD1Fourv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
22145 { 1854 /* ld1 */, AArch64::LD1Fourv8h_POST, Convert__Reg1_2__TypedVectorList4_8161_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_816, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22254 { 1854 /* ld1 */, AArch64::LD1Fourv8h_POST, Convert__Reg1_3__VecListFour1281_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK__DOT_8h, MCK_VecListFour128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_64 }, },
22255 { 1854 /* ld1 */, AArch64::LD1Fourv8h_POST, Convert__Reg1_3__VecListFour1281_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK__DOT_8h, MCK_VecListFour128, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc17455 case AArch64::LD1Fourv8h_POST:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc18171 case AArch64::LD1Fourv8h_POST:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc12709 case AArch64::LD1Fourv8h_POST:
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 443 case AArch64::LD1Fourv8h_POST:
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 3746 SelectPostLoad(Node, 4, AArch64::LD1Fourv8h_POST, AArch64::qsub0);
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 431 { AArch64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 },