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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc14774 { 1854 /* ld1 */, AArch64::LD1Fourv1d_POST, Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
14775 { 1854 /* ld1 */, AArch64::LD1Fourv1d_POST, Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
14848 { 1854 /* ld1 */, AArch64::LD1Fourv1d_POST, Convert__Reg1_3__VecListFour641_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK__DOT_1d, MCK_VecListFour64, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
14849 { 1854 /* ld1 */, AArch64::LD1Fourv1d_POST, Convert__Reg1_3__VecListFour641_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK__DOT_1d, MCK_VecListFour64, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22132 { 1854 /* ld1 */, AArch64::LD1Fourv1d_POST, Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__regXZR, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
22133 { 1854 /* ld1 */, AArch64::LD1Fourv1d_POST, Convert__Reg1_2__TypedVectorList4_1641_0__Tie0_3_3__Reg1_4, AMFBS_HasNEON, { MCK_TypedVectorList4_164, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
22206 { 1854 /* ld1 */, AArch64::LD1Fourv1d_POST, Convert__Reg1_3__VecListFour641_1__Tie0_4_4__regXZR, AMFBS_HasNEON, { MCK__DOT_1d, MCK_VecListFour64, MCK__91_, MCK_GPR64sp, MCK__93_, MCK__HASH_32 }, },
22207 { 1854 /* ld1 */, AArch64::LD1Fourv1d_POST, Convert__Reg1_3__VecListFour641_1__Tie0_4_4__Reg1_5, AMFBS_HasNEON, { MCK__DOT_1d, MCK_VecListFour64, MCK__91_, MCK_GPR64sp, MCK__93_, MCK_GPR64 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc17377 case AArch64::LD1Fourv1d_POST:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc18093 case AArch64::LD1Fourv1d_POST:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc12703 case AArch64::LD1Fourv1d_POST:
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 437 case AArch64::LD1Fourv1d_POST:
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 3671 SelectPostLoad(Node, 4, AArch64::LD1Fourv1d_POST, AArch64::dsub0);
3755 SelectPostLoad(Node, 4, AArch64::LD1Fourv1d_POST, AArch64::dsub0);
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 437 { AArch64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 },