|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc15947 { 2495 /* ldff1w */, AArch64::GLDFF1W_IMM_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
15951 { 2495 /* ldff1w */, AArch64::GLDFF1W_IMM_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
15959 { 2495 /* ldff1w */, AArch64::GLDFF1W_IMM_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s4, MCK__93_ }, },
15973 { 2495 /* ldff1w */, AArch64::GLDFF1W_IMM_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s4, MCK__93_ }, },
23305 { 2495 /* ldff1w */, AArch64::GLDFF1W_IMM_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
23309 { 2495 /* ldff1w */, AArch64::GLDFF1W_IMM_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK__93_ }, },
23317 { 2495 /* ldff1w */, AArch64::GLDFF1W_IMM_REAL, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s4, MCK__93_ }, },
23331 { 2495 /* ldff1w */, AArch64::GLDFF1W_IMM_REAL, Convert__SVEVectorList1321_0__SVEPredicate3bAnyReg1_1__SVEVectorSReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorList132, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorSReg, MCK_UImm5s4, MCK__93_ }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc16901 case AArch64::GLDFF1W_IMM_REAL:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc17617 case AArch64::GLDFF1W_IMM_REAL:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 7340 case AArch64::GLDFF1W_IMM_REAL: {