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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc15949 { 2495 /* ldff1w */, AArch64::GLDFF1W_D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
15953 { 2495 /* ldff1w */, AArch64::GLDFF1W_D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
15967 { 2495 /* ldff1w */, AArch64::GLDFF1W_D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
15981 { 2495 /* ldff1w */, AArch64::GLDFF1W_D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
23307 { 2495 /* ldff1w */, AArch64::GLDFF1W_D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
23311 { 2495 /* ldff1w */, AArch64::GLDFF1W_D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
23325 { 2495 /* ldff1w */, AArch64::GLDFF1W_D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
23339 { 2495 /* ldff1w */, AArch64::GLDFF1W_D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc16885 case AArch64::GLDFF1W_D_IMM_REAL:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc17601 case AArch64::GLDFF1W_D_IMM_REAL:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 7339 case AArch64::GLDFF1W_D_IMM_REAL: