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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc15247 { 1963 /* ld1sw */, AArch64::GLD1SW_D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
15249 { 1963 /* ld1sw */, AArch64::GLD1SW_D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
15257 { 1963 /* ld1sw */, AArch64::GLD1SW_D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
15265 { 1963 /* ld1sw */, AArch64::GLD1SW_D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
22605 { 1963 /* ld1sw */, AArch64::GLD1SW_D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
22607 { 1963 /* ld1sw */, AArch64::GLD1SW_D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__imm_95_0, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK__93_ }, },
22615 { 1963 /* ld1sw */, AArch64::GLD1SW_D_IMM_REAL, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
22623 { 1963 /* ld1sw */, AArch64::GLD1SW_D_IMM_REAL, Convert__SVEVectorList1641_0__SVEPredicate3bAnyReg1_1__SVEVectorDReg1_5__UImm5s41_6, AMFBS_HasSVE, { MCK_SVEVectorList164, MCK_SVEPredicate3bAnyReg, MCK__47_, MCK_z, MCK__91_, MCK_SVEVectorDReg, MCK_UImm5s4, MCK__93_ }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc16677 case AArch64::GLD1SW_D_IMM_REAL:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc17393 case AArch64::GLD1SW_D_IMM_REAL:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 7326 case AArch64::GLD1SW_D_IMM_REAL: