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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc13497 { 971 /* eon */, AArch64::EOR_ZI, Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm16Not1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVELogicalImm16Not }, },
13498 { 971 /* eon */, AArch64::EOR_ZI, Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm32Not1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVELogicalImm32Not }, },
13499 { 971 /* eon */, AArch64::EOR_ZI, Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm64Not1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_LogicalImm64Not }, },
13500 { 971 /* eon */, AArch64::EOR_ZI, Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm8Not1_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVELogicalImm8Not }, },
13508 { 975 /* eor */, AArch64::EOR_ZI, Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm161_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVELogicalImm16 }, },
13510 { 975 /* eor */, AArch64::EOR_ZI, Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm321_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVELogicalImm32 }, },
13511 { 975 /* eor */, AArch64::EOR_ZI, Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm641_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_LogicalImm64 }, },
13514 { 975 /* eor */, AArch64::EOR_ZI, Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm81_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVELogicalImm8 }, },
20855 { 971 /* eon */, AArch64::EOR_ZI, Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm16Not1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVELogicalImm16Not }, },
20856 { 971 /* eon */, AArch64::EOR_ZI, Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm32Not1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVELogicalImm32Not }, },
20857 { 971 /* eon */, AArch64::EOR_ZI, Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm64Not1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_LogicalImm64Not }, },
20858 { 971 /* eon */, AArch64::EOR_ZI, Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm8Not1_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVELogicalImm8Not }, },
20866 { 975 /* eor */, AArch64::EOR_ZI, Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm161_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVELogicalImm16 }, },
20868 { 975 /* eor */, AArch64::EOR_ZI, Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm321_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVELogicalImm32 }, },
20869 { 975 /* eor */, AArch64::EOR_ZI, Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm641_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_LogicalImm64 }, },
20872 { 975 /* eor */, AArch64::EOR_ZI, Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm81_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVELogicalImm8 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc16412 case AArch64::EOR_ZI:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc17128 case AArch64::EOR_ZI:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc15148 case AArch64::EOR_ZI: