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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc13489 { 966 /* dupm */, AArch64::DUPM_ZI, Convert__SVEVectorHReg1_0__SVELogicalImm161_1, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVELogicalImm16 }, },
13490 { 966 /* dupm */, AArch64::DUPM_ZI, Convert__SVEVectorSReg1_0__SVELogicalImm321_1, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVELogicalImm32 }, },
13491 { 966 /* dupm */, AArch64::DUPM_ZI, Convert__SVEVectorDReg1_0__LogicalImm641_1, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_LogicalImm64 }, },
13492 { 966 /* dupm */, AArch64::DUPM_ZI, Convert__SVEVectorBReg1_0__SVELogicalImm81_1, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVELogicalImm8 }, },
16542 { 3356 /* mov */, AArch64::DUPM_ZI, Convert__SVEVectorHReg1_0__SVEPreferredLogicalImm161_1, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPreferredLogicalImm16 }, },
16546 { 3356 /* mov */, AArch64::DUPM_ZI, Convert__SVEVectorSReg1_0__SVEPreferredLogicalImm321_1, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPreferredLogicalImm32 }, },
16551 { 3356 /* mov */, AArch64::DUPM_ZI, Convert__SVEVectorDReg1_0__SVEPreferredLogicalImm641_1, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPreferredLogicalImm64 }, },
20847 { 966 /* dupm */, AArch64::DUPM_ZI, Convert__SVEVectorHReg1_0__SVELogicalImm161_1, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVELogicalImm16 }, },
20848 { 966 /* dupm */, AArch64::DUPM_ZI, Convert__SVEVectorSReg1_0__SVELogicalImm321_1, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVELogicalImm32 }, },
20849 { 966 /* dupm */, AArch64::DUPM_ZI, Convert__SVEVectorDReg1_0__LogicalImm641_1, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_LogicalImm64 }, },
20850 { 966 /* dupm */, AArch64::DUPM_ZI, Convert__SVEVectorBReg1_0__SVELogicalImm81_1, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVELogicalImm8 }, },
23900 { 3356 /* mov */, AArch64::DUPM_ZI, Convert__SVEVectorHReg1_0__SVEPreferredLogicalImm161_1, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEPreferredLogicalImm16 }, },
23904 { 3356 /* mov */, AArch64::DUPM_ZI, Convert__SVEVectorSReg1_0__SVEPreferredLogicalImm321_1, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEPreferredLogicalImm32 }, },
23909 { 3356 /* mov */, AArch64::DUPM_ZI, Convert__SVEVectorDReg1_0__SVEPreferredLogicalImm641_1, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEPreferredLogicalImm64 }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc16020 case AArch64::DUPM_ZI:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc16736 case AArch64::DUPM_ZI:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc14324 case AArch64::DUPM_ZI: {
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp 1819 if (Inst.getOpcode() != AArch64::DUPM_ZI)