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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc12815 { 120 /* and */, AArch64::AND_ZI, Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm161_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVELogicalImm16 }, },
12817 { 120 /* and */, AArch64::AND_ZI, Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm321_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVELogicalImm32 }, },
12818 { 120 /* and */, AArch64::AND_ZI, Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm641_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_LogicalImm64 }, },
12821 { 120 /* and */, AArch64::AND_ZI, Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm81_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVELogicalImm8 }, },
12923 { 288 /* bic */, AArch64::AND_ZI, Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm16Not1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVELogicalImm16Not }, },
12925 { 288 /* bic */, AArch64::AND_ZI, Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm32Not1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVELogicalImm32Not }, },
12926 { 288 /* bic */, AArch64::AND_ZI, Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm64Not1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_LogicalImm64Not }, },
12929 { 288 /* bic */, AArch64::AND_ZI, Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm8Not1_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVELogicalImm8Not }, },
20173 { 120 /* and */, AArch64::AND_ZI, Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm161_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVELogicalImm16 }, },
20175 { 120 /* and */, AArch64::AND_ZI, Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm321_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVELogicalImm32 }, },
20176 { 120 /* and */, AArch64::AND_ZI, Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm641_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_LogicalImm64 }, },
20179 { 120 /* and */, AArch64::AND_ZI, Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm81_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVELogicalImm8 }, },
20281 { 288 /* bic */, AArch64::AND_ZI, Convert__SVEVectorHReg1_0__Tie0_1_2__SVELogicalImm16Not1_2, AMFBS_HasSVE, { MCK_SVEVectorHReg, MCK_SVEVectorHReg, MCK_SVELogicalImm16Not }, },
20283 { 288 /* bic */, AArch64::AND_ZI, Convert__SVEVectorSReg1_0__Tie0_1_2__SVELogicalImm32Not1_2, AMFBS_HasSVE, { MCK_SVEVectorSReg, MCK_SVEVectorSReg, MCK_SVELogicalImm32Not }, },
20284 { 288 /* bic */, AArch64::AND_ZI, Convert__SVEVectorDReg1_0__Tie0_1_2__LogicalImm64Not1_2, AMFBS_HasSVE, { MCK_SVEVectorDReg, MCK_SVEVectorDReg, MCK_LogicalImm64Not }, },
20287 { 288 /* bic */, AArch64::AND_ZI, Convert__SVEVectorBReg1_0__Tie0_1_2__SVELogicalImm8Not1_2, AMFBS_HasSVE, { MCK_SVEVectorBReg, MCK_SVEVectorBReg, MCK_SVELogicalImm8Not }, },
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc15283 case AArch64::AND_ZI:
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc15999 case AArch64::AND_ZI:
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc15147 case AArch64::AND_ZI: