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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenAsmMatcher.inc 4347 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4349 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4351 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4353 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4355 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4357 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4359 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4361 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_1_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4647 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4649 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4651 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4653 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4655 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4657 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4659 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4661 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_2_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4719 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4721 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4723 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4725 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4727 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4729 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4731 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4733 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_3_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4791 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4793 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4795 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4797 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4799 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4801 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },
4803 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_regXZR, 0, CVT_Done },
4805 { CVT_95_Reg, 4, CVT_95_addVectorListOperands_LT_AArch64Operand_COLON__COLON_VecListIdx_95_QReg_44__32_4_GT_, 1, CVT_Tied, Tie1_1_1, CVT_95_addVectorIndexOperands, 2, CVT_Tied, Tie0_4_4, CVT_95_Reg, 6, CVT_Done },